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quad, 16-bit, 2.8 gsps, txdac+? digital-to-analog converter data sheet ad9144 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features supports input data rate >1 gsps proprietary low spurious and distortion design 6-carrier gsm imd = 77 dbc at 75 mhz if sfdr = 82 dbc at dc if, ?9 dbfs flexible 8-lane jesd204b interface support quad or dual dac mode at 2.8 gsps multiple chip synchronization fixed latency data generator latency compensation selectable 1, 2, 4, 8 interpolation filter low power architecture input signal power detection emergency stop for downstream analog circuitry protection transmit enable function allows extra power saving high performance, low noise ph ase-locked loop (pll) clock multiplier digital inverse sinc filter low power: 1.6 w at 1.6 gsps, 1.7 w at 2.0 gsps, full operating conditions 88-lead lfcsp with exposed pad applications wireless communications 3g/4g w-cdma base stations wideband repeaters software defined radios wideband communications point-to-point local multipoint distribution service (lmds) and multichannel multipoint distribution service (mmds) transmit diversity, multiple input/multiple output (mimo) instrumentation automated test equipment general description the ad9144 is a quad, 16-bit, high dynamic range digital-to- analog converter (dac) that provides a maximum sample rate of 2.8 gsps, permitting a multicarrier generation up to the nyquist frequency. the dac outputs are optimized to interface seamlessly with the adrf6720 analog quadrature modulator (aqm) from analog devices, inc. an optional 3-wire or 4-wire serial port interface (spi) provides for programming/readback of many internal parameters. full-scale output current can be programmed over a typical range of 13.9 ma to 27.0 ma. the ad9144 is available in an 88-lead lfcsp. typical application circuit 11675-001 quad dac ad9144 quad mod adrf6720 lpf 0/90 phase shifter jesd204b sysref syncoutx lo_in mod_spi dac dac quad mod adrf6720 lpf 0/90 phase shifter jesd204b syncoutx lo_in mod_spi dac spi clk dac dac figure 1. product highlights 1. greater than 1 ghz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications. 2. advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. jesd204b subclass 1 support simplifies multichip synchronization in software and hardware design. 4. fewer pins for data interface width with a serializer/ deserializer (serdes) jesd204b eight-lane interface. 5. programmable transmit enable function allows easy design balance between power consumption and wake-up time. 6. small package size with 12 mm 12 mm footprint.
ad9144* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad-fmcdaq2-ebz evaluation board ? ad9144 evaluation board documentation data sheet ? ad9144: quad, 16-bit, 2.8 gsps, txdac+? digital-to- analog converter data sheet tools and simulations ? ad9144 ibis model ? ad9144/ad9152/ad9154/ad9135/ad9136 ami model download reference materials informational ? jesd204 serial interface technical articles ? ms-2773: advancement in high speed converter technology enables next-generation wireless communications systems designs design resources ? ad9144 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9144 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad9144 data sheet rev. a | page 2 of 125 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuit ............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 3 ? functional block diagram .............................................................. 4 ? specifications ..................................................................................... 5 ? dc specifications ......................................................................... 5 ? digital specifications ................................................................... 6 ? maximum dac update rate speed specifications by supply ..... 7 ? jesd204b serial interface speed specifications ...................... 7 ? sysref to dac clock timing specifications ......................... 8 ? digital input data timing specifications ................................. 8 ? latency variation specifications ................................................ 9 ? jesd204b interface electrical specifications ........................... 9 ? ac specifications ........................................................................ 10 ? absolute maximum ratings .......................................................... 11 ? thermal resistance .................................................................... 11 ? esd caution ................................................................................ 11 ? pin configuration and function descriptions ........................... 12 ? terminology .................................................................................... 15 ? typical performance characteristics ........................................... 16 ? theory of operation ...................................................................... 21 ? serial port operation ..................................................................... 22 ? data format ................................................................................ 22 ? serial port pin descriptions ...................................................... 22 ? serial port options ..................................................................... 22 ? chip information ............................................................................ 24 ? device setup guide ........................................................................ 25 ? overview ...................................................................................... 25 ? step 1: start up the dac ........................................................... 25 ? step 2: digital datapath ............................................................. 26 ? step 3: transport layer .............................................................. 26 ? step 4: physical layer ................................................................. 27 ? step 5: data link layer .............................................................. 27 ? step 6: optional error monitoring .......................................... 28 ? step 7: optional features ........................................................... 28 ? dac pll setup ........................................................................... 29 ? interpolation ............................................................................... 29 ? jesd204b setup ......................................................................... 29 ? serdes clocks setup ................................................................ 31 ? equalization mode setup .......................................................... 31 ? link latency setup ..................................................................... 31 ? crossbar setup ............................................................................ 33 ? jesd204b serial data interface .................................................... 34 ? jesd204b overview .................................................................. 34 ? physical layer ............................................................................. 35 ? data link layer .......................................................................... 38 ? transport layer .......................................................................... 47 ? jesd204b test modes ............................................................... 60 ? jesd204b error monitoring ..................................................... 61 ? hardware considerations ......................................................... 63 ? digital datapath ............................................................................. 67 ? dual paging ................................................................................. 67 ? data format ................................................................................ 67 ? interpolation filters ................................................................... 67 ? digital modulation ..................................................................... 68 ? inverse sinc ................................................................................. 69 ? digital gain, phase adjust, dc offset, and group delay .... 69 ? i to q swap .................................................................................. 70 ? nco alignment ......................................................................... 70 ? downstream protection ............................................................ 72 ? datapath prbs ........................................................................... 74 ? dc test mode ............................................................................. 74 ? interrupt request operation ........................................................ 75 ? interrupt service routine .......................................................... 75 ? dac input clock configurations ................................................ 76 ? driving the clk inputs .......................................................... 76 ? dac pll fixed register writes ............................................... 76 ? clock multiplication .................................................................. 76 ? starting the pll .......................................................................... 78 ? analog outputs............................................................................... 79 ? transmit dac operation .......................................................... 79 ? device power dissipation .............................................................. 82 ? temperature sensor ................................................................... 82 ? start-up sequence .......................................................................... 83 ? step 1: start up the dac ........................................................... 83 ? step 2: digital datapath ............................................................. 83 ? step 3: transport layer .............................................................. 84 ?
data sheet ad9144 rev. a | page 3 of 125 step 4: physical layer .................................................................. 84 ? step 5: data link layer .............................................................. 85 ? step 6: error monitoring ............................................................ 85 ? register maps and descriptions .................................................... 86 ? device configuration register map ......................................... 86 ? device configuration register descriptions .......................... 94 ? outline dimensions ...................................................................... 124 ? ordering guide ......................................................................... 125 revision history 6/15rev. 0 to rev. a changed functional block diagram section to typical application circuit section .............................................................. 1 changes to figure 1 ........................................................................... 1 changed detailed functional block diagram section to functional block diagram section ................................................. 4 deleted reference voltage parameter, table 1 .............................. 5 changes to output voltage (v out ) logic high parameter, output voltage (v out ) logic low parameter, and sysref frequency parameter, table 2 .......................................................... 6 changes to table 4 ............................................................................ 7 changes to interpolation parameter, table 6 ................................ 8 deleted sync off, subclass mode 0 parameter, table 7 ............... 9 changed junction temperature parameter to operating junction temperature, table 10 .................................................... 11 changes to terminology section .................................................. 15 changes to figure 26 caption ....................................................... 19 changes to figure 29 caption ....................................................... 20 change to device revision parameter, table 14 ......................... 24 changes to step 1: start up the dac section, table 16, and table 17 ............................................................................................. 25 changes to step 3: transport layer section and table 19 ......... 26 changes to table 20 and table 21 ................................................. 27 changes to step 7: optional features section ............................. 28 added table 25; renumbered sequentially ................................. 29 changes to dac pll setup section and table 26 ...................... 29 changes to lane0checksum section ........................................... 30 changes to table 30 and subclass 0 section ................................ 31 changes to table 33 ........................................................................ 32 changes to table 37 ........................................................................ 35 changes to table 38 ........................................................................ 36 added serdes pll fixed register writes section and table 39 ............................................................................................. 36 changes to figure 38 and table 40 ............................................... 37 changes to figure 29 and data link layer section ................... 38 added figure 42; renumbered sequentially ............................... 39 changes to figure 44 ...................................................................... 40 changes to continuous sync mode (syncmod = 0x2) section .............................................................................................. 42 changes to subclass 0 section ....................................................... 43 changes to figure 53 ...................................................................... 50 changes to table 49 and figure 54 ............................................... 51 changes to table 50 and figure 55 ............................................... 52 changes to table 51 and figure 56 ............................................... 53 changes to table 52 and figure 57 ............................................... 54 changes to table 53, table 54, and figure 58 ............................. 55 changes to table 55 and figure 59 ............................................... 56 changes to table 56 and figure 60 ............................................... 57 changes to table 57 and figure 61 ............................................... 58 changes to table 58 and figure 62 ............................................... 59 changes to power supply recommendations section ............... 63 added figure 64 .............................................................................. 64 changes to figure 68 ...................................................................... 66 changes to table 66 ........................................................................ 67 changes to table 70, table 71, table 72, and i to q swap section .............................................................................................. 70 changes to power detection and protection section ................ 72 changes to dc test mode section ............................................... 73 moved figure 75 and table 78 ...................................................... 75 deleted table 80; renumbered sequentially ............................... 76 added dac pll fixed register writes section and table 79 ............................................................................................. 76 changes to clock multiplication section .................................... 76 added loop filter section and charge pump section .............. 77 added temperature tracking section and table 83 .................. 78 changes to starting the pll section and figure 79 ................... 78 changes to transmit dac operation section ............................ 79 changes to self calibration section ............................................. 81 added figure 86 and figure 87 ..................................................... 81 changes to device power dissipation section ............................ 82 changes to table 88 and table 89 ................................................. 83 changes to table 93 ........................................................................ 84 changes to table 94, table 95, and table 96 ............................... 85 changes to table 97 ........................................................................ 86 changes to table 98 ........................................................................ 94 deleted lookup tables for three different dac pll reference frequencies section and table 96 to table 98 ........................... 122 added figure 89 ............................................................................ 124 updated outline dimensions ...................................................... 124 changes to ordering guide ......................................................... 125 7/14revision 0: initial version
ad9144 data sheet rev. a | page 4 of 125 functional block diagram 11675-002 sdio sclk cs irq reset syncout0? syncout0+ protect_out1 protect_out0 dac pll serdes pll power-on reset serial i/o port config registers clk_sel pll_ctrl dacclk pll_lock synchronization logic dac align detect hb1 txen0 txen1 serdin7 v tt serdin0 c l o c k d a t a r e c o v e r y a n d c l o c k f o r m a t t e r syncout1+ syncout1? ref and bias i120 sysref+ sysref? sdo hb3 hb2 dacclk out3+ out3? i n v s i n c f dac 4, 8 nco complex modulation phase adjust q-gain i-gain sysref rx clk+ clk? mode control dacclk clk rx hb3 hb2 hb1 q-offset i-offset hb1 hb3 hb2 mode control hb3 hb2 hb1 fsc fsc out2+ out2? dacclk out1+ out1? i n v s i n c f dac 4, 8 nco complex modulation phase adjust q-gain i-gain q-offset i-offset fsc fsc out0+ out0? clock distribution and control logic p d p 1 p d p 0 figure 2.
data sheet ad9144 rev. a | page 5 of 125 specifications dc specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit resolution 16 bits accuracy with calibration differential nonlinearity (dnl) 1.0 lsb integral nonlinearity (inl) 2.0 lsb main dac outputs gain error with internal reference ?2.5 +2 +5.5 % fsr i/q gain mismatch ?0.6 +0.6 % fsr full-scale output current based on a 4 k external resistor between i120 and gnd maximum setting 25.5 27.0 28.6 ma minimum setting 13.1 13.9 14.8 ma output compliance range ?250 +750 mv output resistance 0.2 m output capacitance 3.0 pf gain dac monotonicity guaranteed settling time to within 0.5 lsb 20 ns main dac temperature drift offset 0.04 ppm gain 32 ppm/c reference internal reference voltage 1.2 v analog supply voltages avdd33 3.13 3.3 3.47 v pvdd12 1.14 1.2 1.26 v cvdd12 1.14 1.2 1.26 v digital supply voltages siovdd33 3.13 3.3 3.47 v v tt 1.1 1.2 1.37 v dvdd12 1.14 1.2 1.26 v 1.274 1.3 1.326 v svdd12 1.14 1.2 1.26 v 1.274 1.3 1.326 v iovdd 1.71 1.8 3.47 v power consumption 4 interpolation mode, jesd mode 4, 8 serdes lanes f dac = 1.6 gsps, if = 40 mhz, nco off, pll on, digital gain on, inverse sinc on, dac fsc = 20 ma 1.59 1.84 w avdd33 126 134 ma pvdd12 95.3 112.4 ma cvdd12 101 111 ma svdd12 includes v tt 518.2 654 ma dvdd12 234 255 ma siovdd33 11 12 ma iovdd 36 50 a
ad9144 data sheet rev. a | page 6 of 125 digital specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ max unit cmos input logic level input voltage (v in ) logic high 1.8 v ? iovdd ? 3.3 v 0.7 iovdd v low 1.8 v ? iovdd ? 3.3 v 0.3 iovdd v cmos output logic level output voltage (v out ) logic high 1.8 v ? iovdd ? 3.3 v 0.75 iovdd v low 1.8 v ? iovdd ? 3.3 v 0.25 iovdd v maximum dac update rate 1 1 interpolation 2 (see table 4) 1060 msps 2 interpolation 3 2120 msps 4 interpolation 2800 msps 8 interpolation 2800 msps adjusted dac update rate 1 interpolation 1060 msps 2 interpolation 1060 msps 4 interpolation 700 msps 8 interpolation 350 msps interface 4 number of jesd204b lanes 8 lanes jesd204b serial interface speed minimum per lane 1.44 gbps maximum per lane, svdd12 = 1.3 v 2% 10.6 gbps dac clock input (clk+, clk?) differential peak-to-peak voltage 400 1000 2000 mv common-mode voltage self biased input, ac-coupled 600 mv maximum clock rate 2800 mhz refclk frequency (pll mode) 6.0 ghz f vco 12.0 ghz 35 1000 mhz system reference input (sysref+, sysref?) differential peak-to-peak voltage 400 1000 2000 mv common-mode voltage 0 2000 mv sysref frequency 5 f data /(k s) hz sysref to dac clock 6 sysref differential swing = 0.4 v, slew rate = 1.3 v/ns, common modes tested: ac-coupled, 0 v, 0.6 v, 1.25 v, 2.0 v setup time t ssd 131 ps hold time t hsd 119 ps keep out window kow 20 ps spi maximum clock rate sclk iovdd = 1.8 v 10 mhz minimum sclk pulse width high t pwh 8 ns low t pwl 12 ns sdio to sclk setup time t ds 5 ns hold time t dh 2 ns
data sheet ad9144 rev. a | page 7 of 125 parameter symbol test conditions/comments min typ max unit sdo to sclk data valid window t dv 25 ns cs to sclk setup time t s cs 5 ns hold time t h cs 2 ns 1 see table 3 for detailed specificatio ns for dac update rate conditions. 2 maximum speed for 1 interpolation is limited by the jesd interface. see table 4 for details. 3 maximum speed for 2 interpolation is limited by the jesd interface. see table 4 for details. 4 see table 4 for detailed specific ations for jesd speed conditions. 5 k, f, and s are jesd204b transport layer parame ters. see table 44 for the full definitions. 6 see table 5 for detailed specifications for sysref to dac clock timing conditions. maximum dac update rate speed specifications by supply avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit maximum dac update rate dvdd12, cvdd12 = 1.2 v 5% 2.23 gsps dvdd12, cvdd12 = 1.2 v 2% 2.41 gsps dvdd12, cvdd12 = 1.3 v 2% 2.80 gsps jesd204b serial interfac e speed specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 4. parameter test conditions/comments min typ max unit half rate svdd12 = 1.2 v 5% 5.75 8.92 gbps svdd12 = 1.2 v 2% 5.75 9.42 gbps svdd12 = 1.3 v 2% 5.75 10.64 gbps full rate svdd12 = 1.2 v 5% 2.88 4.63 gbps svdd12 = 1.2 v 2% 2.88 4.93 gbps svdd12 = 1.3 v 2% 2.88 5.52 gbps oversampling svdd12 = 1.2 v 5% 1.44 2.31 gbps svdd12 = 1.2 v 2% 1.44 2.46 gbps svdd12 = 1.3 v 2% 1.44 2.76 gbps
ad9144 data sheet rev. a | page 8 of 125 sysref to dac clock timing specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, sysref common-mode voltages = 0.0 v, 0.6 v, 1.25 v, and 2.0 v, unless otherwise noted. table 5. parameter test conditions/comments min typ max unit sysref differential swing = 0.4 v, slew rate = 1.3 v/ns setup time ac-coupled 126 ps dc-coupled 131 ps hold time ac-coupled 92 ps dc-coupled 119 ps sysref differential swing = 0.7 v, slew rate = 2.28 v/ns setup time ac-coupled 96 ps dc-coupled 104 ps hold time ac-coupled 77 ps dc-coupled 95 ps sysref swing = 1.0 v, slew rate = 3.26 v/ns setup time ac-coupled 83 ps dc-coupled 90 ps hold time ac-coupled 68 ps dc-coupled 84 ps digital input data timing specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = 25c, i outfs = 20 ma, unless otherwise noted. table 6. parameter test conditions/comments min typ max unit latency interface 17 pclock 1 cycles interpolation 1 58 dac clock cycles 2 137 dac clock cycles 4 251 dac clock cycles 8 484 dac clock cycles inverse sinc 17 dac clock cycles fine modulation 20 dac clock cycles coarse modulation f s /8 8 dac clock cycles f s /4 4 dac clock cycles digital phase adjust 12 dac clock cycles digital gain adjust 12 dac clock cycles power-up time dual a only register 0x011 from 0x60 to 0x00 60 s dual b only register 0x011 from 0x18 to 0x00 60 s all dacs register 0x011 from 0x7c to 0x00 60 s 1 pclock is the ad9144 internal processing clock and equals the lane rate 40.
data sheet ad9144 rev. a | page 9 of 125 latency variation specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = 25c, i outfs = 20 ma, unless otherwise noted. table 7. parameter min typ max unit dac latency variation sync on pll off 0 1 dacclk cycles pll on ?1 +1 dacclk cycles jesd204b interface electrical specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 8. parameter symbol test conditions/comments min typ max unit jesd204b data inputs input leakage current 25c logic high input level = 1.2 v 0.25 v, v tt = 1.2 v 10 a logic low input level = 0 v ?4 a unit interval ui 94 714 ps common-mode voltage v rcm ac-coupled, v tt = svdd12 1 ?0.05 +1.85 v differential voltage r_v diff 110 1050 mv v tt source impedance z tt at dc 30 differential impedance z rdiff at dc 80 100 120 differential return loss rl rdif 8 db common-mode return loss rl rcm 6 db differential outputs (syncout ) 2 output differential voltage v od normal swing mode: register 0x2a5[0] = 0 192 235 mv output offset voltage v os 1.19 1.27 v output differential voltage v od high swing mode: register 0x2a5[0] = 1 341 394 mv deterministic latency fixed 17 pclock 3 cycles variable 2 pclock 3 cycles sysref-to-lmfc delay 4 dac clock cycles 1 as measured on the input side of the ac coupling capacitor. 2 ieee standard 1596.3 lvds compatible. 3 pclock is the ad9144 internal processing clock and equals the lane rate 40.
ad9144 data sheet rev. a | page 10 of 125 ac specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, 1 v tt = 1.2 v, t a = 25c, i outfs = 20 ma, unless otherwise noted. table 9. parameter test conditions/comments min typ max unit spurious-free dynamic range (sfdr) ?9 dbfs single-tone f dac = 983.04 msps f out = 20 mhz 82 dbc f dac = 983.04 msps f out = 150 mhz 76 dbc f dac = 1966.08 msps f out = 20 mhz 81 dbc f dac = 1966.08 msps f out = 170 mhz 69 dbc two-tone intermodulation distortion (imd) ?9 dbfs f dac =983.04 msps f out = 20 mhz 90 dbc f dac = 983.04 msps f out = 150 mhz 82 dbc f dac = 1966.08 msps f out = 20 mhz 90 dbc f dac = 1966.08 msps f out = 170 mhz 81 dbc noise spectral density (nsd), single-tone 0 dbfs f dac = 983.04 msps f out = 150 mhz ?162 dbm/hz f dac = 1966.08 msps f out = 150 mhz ?163 dbm/hz w-cdma first adjacent channel leakage ratio (aclr), single carrier 0 dbfs f dac = 983.04 msps f out = 30 mhz 82 dbc f dac = 983.04 msps f out = 150 mhz 80 dbc f dac = 1966.08 msps f out = 150 mhz 80 dbc w-cdma second aclr, single carrier 0 dbfs f dac = 983.04 msps f out = 30 mhz 84 dbc f dac = 983.04 msps f out = 150 mhz 85 dbc f dac = 1966.08 msps f out = 150 mhz 85 dbc 1 svdd12 = 1.3 v for all f dac = 1966.08 msps conditions in table 9.
data sheet ad9144 rev. a | page 11 of 125 absolute maximum ratings table 10. parameter rating i120 to ground ?0.3 v to avdd33 + 0.3 v serdinx, v tt , syncout1 / syncout0 , txenx ?0.3 v to siovdd33 + 0.3 v outx ?0.3 v to avdd33 + 0.3 v sysref gnd ? 0.5 v to +2.5 v clk to ground ?0.3 v to pvdd12 + 0.3 v reset , irq , cs , sclk, sdio, sdo, protect_outx to ground ?0.3 v to iovdd + 0.3 v ldo_byp1 ?0.3 v to svdd12 + 0.3 v ldo_byp2 ?0.3 v to pvdd12 + 0.3 v ldo24 ?0.3 v to avdd33 + 0.3 v ambient operating temperature (t a ) ?40c to +85c operating junction temperature 125c storage temperature ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance the exposed pad (epad) must be soldered to the ground plane for the 88-lead lfcsp. the epad provides an electrical, thermal, and mechanical connection to the board. typical ja , jb , and jc values are specified for a 4-layer jesd51-7 high effective thermal conductivity test board for leaded surface-mount packages. ja is obtained in still air conditions (jesd51-2). airflow increases heat dissipation, effectively reducing ja . jb is obtained following double-ring cold plate test conditions (jesd51-8). jc is obtained with the test case temperature moni- tored at the bottom of the exposed pad. jt and jb are thermal characteristic parameters obtained with ja in still air test conditions. junction temperature (t j ) can be estimated using the following equations: t j = t t + ( jt p ), or t j = t b + ( jb p ) where: t t is the temperature measured at the top of the package. p is the total device power dissipation. t b is the temperature measured at the board. table 11. thermal resistance package ja jb jc jt jb unit 88-lead lfcsp 1 22.6 5.59 1.17 0.1 5.22 c/w 1 the exposed pad must be securely connected to the ground plane. esd caution
ad9144 data sheet rev. a | page 12 of 125 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pvdd12 clk+ clk? pvdd12 sysref+ sysref? pvdd12 pvdd12 pvdd12 notes 1. the exposed pad must be securely connected to the ground plane. pvdd12 txen0 txen1 dvdd12 dvdd12 serdin0+ serdin0? 17 svdd12 18 serdin1+ 19 serdin1? 20 svdd12 23 24 25 26 27 28 29 30 31 32 33 34 36 37 syncout0+ syncout0? v tt serdin2+ serdin2? svdd12 serdin3+ serdin3? svdd12 svdd12 svdd12 ldo_byp1 35 siovdd33 svdd12 serdin4? 38 serdin4+ 39 svdd12 40 serdin5? 41 serdin5+ 58 57 56 55 54 53 52 51 50 49 48 47 46 45 protect_out1 59 protect_out0 60 irq 61 reset 62 sdo 63 sdio 64 sclk 65 cs 66 iovdd pvdd12 pvdd12 gnd gnd dvdd12 serdin7+ serdin7? svdd12 serdin6+ serdin6? svdd12 v tt svdd12 78 77 76 75 74 73 72 71 70 69 68 67 out1+ out1? 79 80 ldo24 81 cvdd12 82 ldo24 83 out0? 84 out0+ 85 avdd33 86 i120 87 cvdd12 88 ldo_byp2 avdd33 cvdd12 avdd33 out2+ out2? ldo24 cvdd12 ldo24 out3? out3+ avdd33 21 v tt 22 svdd12 42 v tt 43 syncout1? 44 syncout1+ ad9144 top view (not to scale) 11675-003 figure 3. pin configuration table 12. pin function descriptions pin no. mnemonic description 1 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 2 clk+ pll reference/clock input, positive. when the pll is used , this pin is the positive re ference clock input. when the pll is not used, this pin is the positive device clock input. this pin is self biased and must be ac-coupled. 3 clk? pll reference/clock input, negative. when the pll is used, this pin is the negative re ference clock input. when the pll is not used, this pin is the negative device clock input. this pin is self biased and must be ac-coupled. 4 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 5 sysref+ positive reference clock for deterministic latency. this pin is self biased for ac coupling. it can be ac-coupled or dc-coupled. 6 sysref? negative reference clock for deterministic latency. this pin is self biased for ac coupling. it can be ac-coupled or dc-coupled. 7 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 8 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 9 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 10 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 11 txen0 transmit enable for dac0 and dac1. the cmos levels are determined with respect to iovdd. 12 txen1 transmit enable for dac2 and dac3. the cmos levels are determined with respect to iovdd. 13 dvdd12 1.2 v digital supply. 14 dvdd12 1.2 v digital supply. 15 serdin0+ serial channel input 0, positive. cml compliant. serdin0+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 16 serdin0? serial channel input 0, negative. cml compliant. serdin0? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 17 svdd12 1.2 v jesd204b receiver supply. 18 serdin1+ serial channel input 1, positive. cml compliant. serdin1+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 19 serdin1? serial channel input 1, negative. cml compliant. serdin1? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only.
data sheet ad9144 rev. a | page 13 of 125 pin no. mnemonic description 20 svdd12 1.2 v jesd204b receiver supply. 21 v tt 1.2 v termination voltage. connect v tt to the svdd12 supply pins. 22 svdd12 1.2 v jesd204b receiver supply. 23 syncout0+ positive lvds sync (active low) output signal channel link 0. 24 syncout0? negative lvds sync (active low) output signal channel link 0. 25 v tt 1.2 v termination voltage. connect v tt to the svdd12 supply pins. 26 serdin2+ serial channel input 2, positive. cml compliant. serdin2+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 27 serdin2? serial channel input 2, negative. cml compliant. serdin2? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 28 svdd12 1.2 v jesd204b receiver supply. 29 serdin3+ serial channel input 3, positive. cml compliant. serdin3+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 30 serdin3? serial channel input 3, negative. cml compliant. serdin3? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 31 svdd12 1.2 v jesd204b receiver supply. 32 svdd12 1.2 v jesd204b receiver supply. 33 svdd12 1.2 v jesd204b receiver supply. 34 ldo_byp1 ldo serdes bypass. this pin requires a 1 resistor in series with a 1 f capacitor to ground. 35 siovdd33 3.3 v supply for serdes. 36 svdd12 1.2 v jesd204b receiver supply. 37 serdin4? serial channel input 4, negative. cml compliant. serdin4? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 38 serdin4+ serial channel input 4, positive. cml compliant. serdin4+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 39 svdd12 1.2 v jesd204b receiver supply. 40 serdin5? serial channel input 5, negative. cml compliant. serdin5? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 41 serdin5+ serial channel input 5, positive. cml compliant. serdin5+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 42 v tt 1.2 v termination voltage. connect v tt to the svdd12 supply pins. 43 syncout1? negative lvds sync (active low) output signal channel link 1. 44 syncout1+ positive lvds sync (active low) output signal channel link 1. 45 svdd12 1.2 v jesd204b receiver supply. 46 v tt 1.2 v termination voltage. connect v tt to the svdd12 supply pins. 47 svdd12 1.2 v jesd204b receiver supply. 48 serdin6? serial channel input 6, negative. cml compliant. serdin6? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 49 serdin6+ serial channel input 6, positive. cml compliant. serdin6+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 50 svdd12 1.2 v jesd204b receiver supply. 51 serdin7? serial channel input 7, negative. cml compliant. serdin7? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 52 serdin7+ serial channel input 7, positive. cml compliant. serdin7+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac-coupled only. 53 dvdd12 1.2 v digital supply. 54 gnd ground. connect gnd to the ground plane. 55 gnd ground. connect gnd to the ground plane. 56 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 57 pvdd12 1.2 v supply. pvdd12 provides a clean supply. 58 protect_out1 power detection protection pin output for dac2 and dac3. pin 58 is high when power protection is in process. 59 protect_out0 power detection protection pin output for dac0 and dac1. pin 59 is high when power protection is in process. 60 irq interrupt request (active low, open drain). 61 reset reset. this pin is active low. cmos levels are determined with respect to iovdd.
ad9144 data sheet rev. a | page 14 of 125 pin no. mnemonic description 62 sdo serial port data output. cmos levels are determined with respect to iovdd. 63 sdio serial port data input/output. cmos le vels are determined with respect to iovdd. 64 sclk serial port clock input. cmos levels are determined with respect to iovdd. 65 cs serial port chip select. this pin is active low; cmos levels are determined with respect to iovdd. 66 iovdd iovdd supply for cmos input/output and spi. operational for 1.8 v ? iovdd ? 3.3 v. 67 avdd33 3.3 v analog supply for dac cores. 68 out3+ dac3 positive current output. 69 out3? dac3 negative current output. 70 ldo24 2.4 v ldo. requires a 1 f capacitor to ground. 71 cvdd12 1.2 v clock supply. place bypass capacitors as near as possible to pin 71. 72 ldo24 2.4 v ldo. requires a 1 f capacitor to ground. 73 out2? dac2 negative current output. 74 out2+ dac2 positive current output. 75 avdd33 3.3 v analog supply for dac cores. 76 cvdd12 1.2 v clock supply. place bypass capacitors as near as possible to pin 76. 77 avdd33 3.3 v analog supply for dac cores. 78 out1+ dac1 positive current output. 79 out1? dac1 negative current output. 80 ldo24 2.4 v ldo. requires a 1 f capacitor to ground. 81 cvdd12 1.2 v clock supply. place bypass capacitors as near as possible to pin 81. 82 ldo24 2.4 v ldo. requires a 1 f capacitor to ground. 83 out0? dac0 negative current output. 84 out0+ dac0 positive current output. 85 avdd33 3.3 v analog supply for dac cores. 86 i120 output current generation pin for dac full-scale current. tie a 4 k resistor from the i120 pin to ground. 87 cvdd12 1.2 v clock supply. place bypass capacitors as near as possible to pin 87. 88 ldo_byp2 ldo clock bypass for dac pll. this pin requires a 1 resistor in series with a 1 f capacitor to ground. epad exposed pad. the exposed pad must be securely connected to the ground plane.
data sheet ad9144 rev. a | page 15 of 125 terminology integral nonlinearity (inl) inl is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error offset error is the deviation of the output current from the ideal of 0 ma. for outx+, 0 ma output is expected when all inputs are set to 0. for outx?, 0 ma output is expected when all inputs are set to 1. gain error gain error is the difference between the actual and ideal output span. the actual span is determined by the difference between the output when the input is at its minimum code and the output when the input is at its maximum code. output compliance range the output compliance range is the range of allowable voltages at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t offset drift is a measure of how far from full-scale range (fsr) the dac output current is at 25c (in ppm). gain drift is a measure of the slope of the dac output current across its full ambient operating temperature range, t a , (in ppm/c). power supply rejection (psr) psr is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac. typically, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the dac output. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. adjusted dac update rate the adjusted dac update rate is defined as the dac update rate divided by the smallest interpolating factor. for clarity on dacs with multiple interpolating factors, the adjusted dac update rate for each interpolating factor may be given. physical lane physical lane x refers to serdinx. logical lane logical lane x refers to physical lanes after optionally being remapped by the crossbar block (register 0x308 to register 0x30b). link lane link lane x refers to logical lanes considered per link. when paging link 0 (register 0x300[2] = 0), link lane x = logical lane x. when paging link 1 (register 0x300[2] = 1, dual-link only), link lane x = logical lane x + 4.
ad9144 data sheet rev. a | page 16 of 125 typical performance characteristics 0 ?100 ?80 ?60 ?40 ?20 0500 400 300 200 100 sfdr (dbc) f out (mhz) f dac = 983mhz f dac = 1228mhz f dac = 1474mhz 11675-104 figure 4. single-tone sfdr vs. f out in the first nyquist zone, f dac = 983 mhz, 1228 mhz, and 1474 mhz 0 ?100 ?80 ?60 ?40 ?20 05 0 0 400 300 200 100 sfdr (dbc) f out (mhz) f dac = 1966mhz f dac = 2456mhz median 11675-305 figure 5. single-tone sfdr vs. f out in the first nyquist zone, f dac = 1966 mhz and 2456 mhz 0 ?100 ?80 ?60 ?40 ?20 0500 400 300 200 100 sfdr (dbc) f out (mhz) in-band second harmonic in-band third harmonic max digital spur 11675-106 figure 6. single-tone second and third harmonics and maximum digital spur in the first nyquist zone, f dac = 1966 mhz, 0 db back off 0 ?20 ?40 ?60 ?80 ?100 sfdr (dbc) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-107 figure 7. single-tone sfdr vs. f out in the first nyquist zone over digital back off, f dac = 983 mhz 0 ?20 ?40 ?60 ?80 ?100 sfdr (dbc) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-108 figure 8. single-tone sfdr vs. f out in the first nyquist zone over digital back off, f dac = 1966 mhz 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) 0 100 200 300 400 500 f out (mhz) f dac = 983mhz f dac = 1228mhz f dac = 1474mhz 11675-109 figure 9. two-tone third imd (imd3) vs. f out , f dac = 983 mhz, 1228 mhz, and 1474 mhz
data sheet ad9144 rev. a | page 17 of 125 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) 0 100 200 300 400 500 f out (mhz) f dac = 1966mhz f dac = 2456mhz 11675-110 figure 10. two-tone third imd (imd3) vs. f out , f dac = 1966 mhz and 2456 mhz 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-111 figure 11. two-tone third imd (imd3) vs. f out over digital back off, f dac = 983 mhz, each tone is at ?6 dbfs 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-112 figure 12. two-tone third imd (imd3) vs. f out over digital back off, f dac = 1966 mhz, each tone is at ?6 dbfs f dac = 983mhz f dac = 1966mhz 1mhz tone spacing 16mhz tone spacing 35mhz tone spacing 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) 0 100 200 300 400 500 f out (mhz) 11675-113 figure 13. two-tone third imd (imd3) vs. f out over tone spacing at 0 db back off, f dac = 983 mhz and 1966 mhz ? 130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 nsd (dbm/hz) f dac = 983mhz f dac = 1228mhz f dac = 1474mhz 0 100 200 300 400 500 f out (mhz) 11675-114 figure 14. single-tone (0 dbfs) nsd vs. f out , f dac = 983 mhz, 1228 mhz, and 1474 mhz ? 130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 nsd (dbm/hz) f dac = 1966mhz f dac = 2456mhz 0 100 200 300 400 500 f out (mhz) 11675-115 figure 15. single-tone (0 dbfs) nsd vs. f out , f dac = 1966 mhz and 2456 mhz
ad9144 data sheet rev. a | page 18 of 125 ? 130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 nsd (dbm/hz) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-116 figure 16. single-tone nsd vs. f out over digital back off, f dac = 983 mhz ? 130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 nsd (dbm/hz) 0 100 200 300 400 500 f out (mhz) 0dbfs ?6dbfs ?9dbfs ?12dbfs 11675-117 figure 17. single-tone nsd vs. f out over digital back off, f dac = 1966 mhz ? 130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 nsd (dbm/hz) 0 100 200 300 400 500 f out (mhz) pll off pll on f dac = 983mhz f dac = 1966mhz 11675-118 figure 18. single-tone nsd (0 dbfs) vs. f out , f dac = 983 mhz and 1966 mhz, pll on and off f out = 30mhz f out = 200mhz f out = 400mhz pll: off pll: on offset frequency (hz) phase noise (dbc/hz) ? 60 ?80 ?100 ?120 ?140 ?160 ?180 10 100 1k 10k 100k 1m 10m offset frequency (hz) 11675-119 figure 19. single-tone phase nois e vs. offset frequency over f out , f dac = 2.0 ghz, pll on and off 11675-315 figure 20. 1c wcdma aclr, f out = 30 mhz, f dac = 983 mhz, 2 interpolation, pll frequency = 122 mhz 11675-316 figure 21. 1c wcdma aclr, f out = 122 mhz, f dac = 983 mhz, 2 interpolation, pll frequency = 122 mhz
data sheet ad9144 rev. a | page 19 of 125 11675-317 figure 22. 4c wcdma aclr, f out = 30 mhz, f dac = 983 mhz, 2 interpolation, pll frequency = 122 mhz 11675-318 figure 23. 4c wcdma aclr, f out = 122 mhz, f dac = 983 mhz, 2 interpolation, pll frequency = 122 mhz 11675-319 figure 24. 4c wcdma aclr, f out = 30 mhz, f dac = 1966 mhz, 4 interpolation, pll frequency = 245 mhz 11675-320 figure 25. 4c wcdma aclr, f out = 245 mhz, f dac = 1966 mhz, 4 interpolation, pll frequency = 245 mhz 1800 1700 1600 1500 1400 1300 1200 1000 1100 500 0 2500 2000 1500 1000 power consumption (mw) f dac (mhz) 11675-326 1 2 4 8 figure 26. total power consumption vs. f dac over interpolation, 8 serdes lanes enabled, 4 dacs enabled, nco, digital gain, inverse sinc and dac pll disabled 120 100 80 60 40 20 0 200 1600 1400 1200 1000 800 600 400 power consumption (mw) f dac (mhz) 11675-327 nco pll ( f dac / f ref ratio:4) digital gain inverse sinc figure 27. power consumption vs. f dac over digital functions
ad9144 data sheet rev. a | page 20 of 125 700 100 200 300 400 500 600 18 765432 svdd12 current (ma) lane rate (gbps) 2 lanes 4 lanes 8 lanes 1.2v svdd12 supply 1.3v svdd12 supply 11675-328 figure 28. svdd12 current vs. lane rate over number of serdes lanes and supply voltage setting 350 0 50 100 150 200 250 300 200 1600 1400 1200 100 800 600 400 supply current (ma) f dac (mhz) pvdd12 avdd33 cvdd12 dvdd12 1.2v supply 3.3v supply 1.3v supply 11675-329 figure 29. dvdd12, cvdd12, pvdd12, and avdd33 supply current vs. f dac over supply voltage setting, 4 dacs enabled
data sheet ad9144 rev. a | page 21 of 125 theory of operation the ad9144 is a 16-bit, quad dac with a serdes interface. figure 2 shows a detailed functional block diagram of the ad9144 . eight high speed serial lanes carry data at a maximum speed of 10.6 gbps, and a 1.06 gsps input data rate to the dacs. compared to either lvds or cmos interfaces, the serdes interface simplifies pin count, board layout, and input clock requirements to the device. the clock for the input data is derived from the device clock (required by the jesd204b specification). this device clock can be sourced with a pll reference clock used by the on-chip pll to generate a dac clock or a high fidelity direct external dac sampling clock. the device can be configured to operate in one-, two-, four-, or eight-lane modes, depending on the required input data rate. to add application flexibility, the quad dac can be configured as a dual-link device with each jesd204b link providing data for a dual dac pair. the digital datapath of the ad9144 offers four interpolation modes (1, 2, 4, and 8) through three half-band filters with a maximum dac sample rate of 2.8 gsps. an inverse sinc filter is provided to compensate for sinc related roll-off. the ad9144 dac cores provide a fully differential current output with a nominal full-scale current of 20 ma. the full-scale current, i outfs , is user adjustable to between 13.9 ma and 27.0 ma, typically. the differential current outputs are complementary and are optimized for easy integration with the analog devices adrf6720 aqm. the ad9144 is capable of multichip synchronization that can both synchronize multiple dacs and establish a constant and deterministic latency (latency locking) path for the dacs. the latency for each of the dacs remains constant from link establishment to link establishment. an external alignment (sysref) signal makes the ad9144 subclass 1 compliant. several modes of sysref signal handling are available for use in the system. an spi configures the various functional blocks and monitors their statuses. the various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the device setup guide section). simple spi initialization routines set up the jesd204b link and are included in the evaluation board package. the following sections describe the various blocks of the ad9144 in greater detail. descriptions of the jesd204b interface, control parameters, and various registers to set up and monitor the device are provided. the recommended start-up routine reliably sets up the data link.
ad9144 data sheet rev. a | page 22 of 125 serial port operation the serial port is a flexible, synchronous serial communications port that allows easy interfacing with many industry-standard microcontrollers and microprocessors. the serial input/output (i/o) is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9144 . msb first or lsb first transfer formats are supported. the serial port interface can be configured as a 4-wire interface or a 3-wire interface in which the input and output share a single- pin i/o (sdio). 64 sclk 63 sdio 62 sdo 65 cs spi port 11675-044 figure 30. serial port interface pins there are two phases to a communication cycle with the ad9144. phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 sclk rising edges. the instruction word provides the serial port controller with information regarding the data transfer cycle, phase 2 of the communication cycle. the phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the following data transfer. a logic high on the cs pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. from this state, the next 16 rising sclk edges represent the instruction bits of the current i/o operation. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one or more data bytes. eight n sclk cycles are needed to transfer n bytes during the transfer cycle. registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word (ftw) and numerically controlled oscillator (nco) phase offsets, which change only when the frequency tuning word ftw_update_req bit is set. data format the instruction byte contains the information shown in table 13. table 13. serial port instruction word i[15] (msb) i[14:0] r/w a[14:0] r/ w , bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction word write. logic 1 indicates a read operation, and logic 0 indicates a write operation. a14 to a0, bit 14 to bit 0 of the instruction word, determine the register that is accessed during the data transfer portion of the communication cycle. for multibyte transfers, a[14:0] is the starting address. the remaining register addresses are generated by the device based on the addrinc bit. if addrinc is set high (register 0x000, bit 5 and bit 2), multibyte spi writes start on a[14:0] and increment by 1 every 8 bits sent/received. if addrinc is set to 0, the address decrements by 1 every 8 bits. serial port pin descriptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and runs the internal state machines. the maximum frequency of sclk is 10 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) an active low input starts and gates a communication cycle. cs allows more than one device to be used on the same serial communications lines. the sdio pin goes to a high impedance state when this input is high. during the communication cycle, chip select must stay low. serial data i/o (sdio) this pin is a bidirectional data line. in 4-wire mode, this pin acts as the data input, and sdo acts as the data output. serial port options the serial port can support both msb first and lsb first data formats. this functionality is controlled by the lsbfirst bit (register 0x000, bit 6 and bit 1). the default is msb first (lsbfirst = 0). when lsbfirst = 0 (msb first), the instruction and data bits must be written from msb to lsb. r/ w is followed by a[14:0] as the instruction word, and d[7:0] is the data-word. when lsbfirst = 1 (lsb first), the opposite is true. a[0:14] is followed by r/ w , which is subsequently followed by d[0:7]. the serial port supports a 3-wire or 4-wire interface. when sdoactive = 1 (register 0x000, bit 4 and bit 3), a 4-wire interface with a separate input pin (sdio) and output pin (sdo) is used. when sdoactive = 0, the sdo pin is unused and the sdio pin is used for both input and output.
data sheet ad9144 rev. a | page 23 of 125 multibyte data transfers can be performed as well. this is done by holding the cs pin low for multiple data transfer cycles (eight sclks) after the first data transfer word following the instruction cycle. the first eight sclks following the instruction cycle read from or write to the register provided in the instruction cycle. for each additional eight sclk cycles, the address is either incremented or decremented and the read/write occurs on the new register. the direction of the address can be set using addrinc (register 0x000, bit 5 and bit 2). when addrinc is 1, the multicycle addresses are incremented. when addrinc is 0, the addresses are decremented. a new write cycle can always be initiated by bringing cs high and then low again. to prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. this is completed independently from the lsb first bit and ensures that there are extra clock cycles following the soft reset bits (register 0x000, bit 0 and bit 7). this only applies when writing to register 0x000. r/w a14 a13 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle s clk sdio cs 11675-045 figure 31. serial register interface timing, msb first, addrinc = 0 a0 a1 a2 a12 a13 a14 d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle s clk sdio cs r/w 11675-046 figure 32. serial register interface timing, lsb first, addrinc = 1 sclk sdio cs data bit n ? 1 data bit n t dv 11675-048 figure 33. timing diagram for serial port register read sclk sdio cs instruction bit 14 instruction bit 0 instruction bit 15 t scs t ds t dh t pwh t pwl t hcs 11675-047 figure 34. timing diagram for serial port register write
ad9144 data sheet rev. a | page 24 of 125 chip information register 0x003 to register 0x006 contain chip information, as shown in table 14. table 14. chip information information description chip type the product type is high speed dac, which is represented by a code of 0x04 in register 0x003. product id 8 msbs in register 0x005 and 8 lsbs in register 0x004. the product id is 0x9144. product grade register 0x006[7:4]. the product grade is 0x00. device revision register 0x006[3:0]. the device revision is 0x06.
data sheet ad9144 rev. a | page 25 of 125 device setup guide overview the sequence of steps to properly set up the ad9144 is as follows: 1. set up the spi interface, power up necessary circuit blocks, make required writes to the configuration registers, and set up the dac clocks (see the step 1: start up the dac section). 2. set the digital features of the ad9144 (see the step 2: digital datapath section). 3. set up the jesd204b links (see the step 3: transport layer section). 4. set up the physical layer of the serdes interface (see the step 4: physical layer section). 5. set up the data link layer of the serdes interface (see the step 5: data link layer section). 6. check for errors (see the step 6: optional error monitoring section). 7. optionally, enable any needed features as described in the step 7: optional features section. the register writes listed in table 15 to table 21 give the register writes necessary to set up the ad9144 . consider printing out this setup guide and filling in the value column with appropriate variable values for the conditions of the desired application. the notation 0x, shaded in gray, indicates register settings that must be filled in by the user. to fill in the unknown register values, select the correct settings for each variable listed in the variable column of table 15 to table 21. the description column describes how to set variables or provides a link to a section where this is described. step 1: start up the dac this section describes how to set up the spi interface, power up necessary circuit blocks, write required configuration registers, and set up the dac clocks, as listed in table 15. table 15. power-up and dac initialization settings addr. bit no. value 1 variable description 0x000 0xbd soft reset. 0x000 0x3c deassert reset, set 4-wire spi. 0x011 0x 7 0 power up band gap. [6:3] pddacs pddacs = 0 if all 4 dacs are being used. if not, see the dac power-down setup section. 2 0 power up master dac. 0x080 0x pdclocks pdclocks = 0 if all 4 dacs are being used. if not, see the dac power-down setup section. 0x081 0x pdsysref pdsysref = 0x00 for subclass 1. pdsysref = 0x10 for subclass 0. see the subclass setup section for details on subclass. 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on sele cting the appropriate register value. the registers in table 16 must be written from their default values to be the values listed in the table for the device to work correctly. these registers must be written after any soft reset, hard reset, or power-up occurs. table 16. required de vice configurations addr. value description 0x12d 0x8b digital da tapath configuration 0x146 0x01 digital da tapath configuration 0x2a4 0xff clock configuration 0x232 0xff serdes interface configuration 0x333 0x01 serdes interface configuration if using the optional dac pll, also set the registers in table 17. table 17. optional dac pll configuration procedure addr. value 1 variable description 0x087 0x62 optimal dac pll loop filter settings 0x088 0xc9 optimal dac pll loop filter settings 0x089 0x0e optimal dac pll loop filter settings 0x08a 0x12 optimal dac pll charge pump settings 0x08d 0x7b optimal dac ldo settings for dac pll 0x1b0 0x00 power dac pll blocks when power machine is disabled 0x1b9 0x24 optimal dac pll charge pump settings 0x1bc 0x0d optimal dac pll vco control settings 0x1be 0x02 optimal dac pll vco power control settings 0x1bf 0x8e optimal dac pll vco calibration settings 0x1c0 0x2a optimal dac pll lock counter length setting 0x1c1 0x2a optimal dac pll charge pump setting 0x1c4 0x7e optimal dac pll varactor settings 0x08b 0x lodivmode see the dac pll setup section 0x08c 0x refdivmode see the dac pll setup section 0x085 0x bcount see the dac pll setup section various 0x lookupvals see table 25 in the dac pll setup section for the list of register addresses and values for each. 0x083 0x10 enable dac pll 2 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the appropriate register value. 2 verify that register 0x084[1] reads back 1 after enabling the dac pll to indicate that the dac pll has locked.
ad9144 data sheet rev. a | page 26 of 125 step 2: digital datapath this section describes which interpolation filters to use and how to set the data format being used. additional digital features are available including fine and coarse modulation, digital gain scaling, and an inverse sinc filter used to improve pass-band flatness. table 22 provides further details on the feature blocks available. table 18. digital datapath settings addr. bit no. value 1 variable description 0x112 0x interpmode select interpolation mode; see the interpolation section. 0x110 0x 7 datafmt data fmt = 0 if twos complement; datafmt = 1 if unsigned binary. 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on se lecting the appropriate register value. step 3: transport layer this section describes how to set up the jesd204b links. the parameters are determined by the desired jesd204b operating mode. see the jesd204b setup section for details. table 19 shows the register settings for the transport layer. if using dual-link mode, perform writes from register 0x300 to register 0x47d with currentlink = 0 and then repeat the same set of register writes with currentlink = 1 (register 0x200 and register 0x201 need only be written once). table 19. transport layer settings addr. bit no. value 1 variable description 0x200 0x00 power up the interface. 0x201 0x unusedlanes see the jesd204b setup section. 0x300 0x 6 checksummode see the jesd204b setup section for details on these variables. 3 duallink 2 currentlink 0x450 0x did set did to match the device id sent by the transmitter. 0x451 0x bid set bid to match the bank id sent by the transmitter. 0x452 0x lid set lid to match the lane id sent by the transmitter. 0x453 0x 7 scrambling see the jesd204b setup section. [4:0] l ? 1 2 0x454 0x f ? 1 2 see the jesd204b setup section. 0x455 0x k ? 1 2 see the jesd204b setup section. 0x456 0x m ? 1 2 see the jesd204b setup section. 0x457 0x n ? 1 2 n = 16. 0x458 0x 5 subclass see the jesd204b setup section. [4:0] np ? 1 2 np = 16. 0x459 0x 5 jesdver jesdver = 1 for jesd204b, jesdver = 0 for jesd204a. [4:0] s ? 1 2 see the jesd204b setup section. 0x45a 0x 7 hd see the jesd204b setup section. [4:0] 0 cf cf must equal 0. 0x45d 0x lane0checksum see the jesd204b setup section. 0x46c 0x lanes deskew lanes. see the jesd204b setup section. 0x476 0x f see the jesd204b setup section. 0x47d 0x lanes enable lanes. 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the correct register value. 2 this jesd204b link parameter is programmed in n ? 1 notation as noted. for example, if the setup requires l = 8 (8 lanes per link), program l ? 1 or 7 into register 0x453[4:0].
data sheet ad9144 rev. a | page 27 of 125 step 4: physical layer this section describes how to set up the physical layer of the serdes interface. in this section, the input termination settings are configured along with the cdr sampling and serdes pll. table 20. device configurations and physical layer settings addr. bit no. value 1 variable description 0x2aa 0xb7 serdes interface termination setting 0x2ab 0x87 0x2b1 0xb7 serdes interface termination setting 0x2b2 0x87 0x2a7 0x01 autotune phy setting 0x2ae 0x01 autotune phy setting 0x314 0x01 serdes spi configuration 0x230 0x 5 halfrate set up cdr; see the serdes clocks setup section [4:2] 0x2 serdes pll default configuration 1 ovsmp set up cdr; see the serdes clocks setup section 0x206 0x00 reset cdr 0x206 0x01 release cdr reset 0x289 0x 2 1 serdes pll configuration [1:0] plldiv set cdr oversampling for pll; see the serdes clocks setup section 0x284 0x62 optimal serdes pll loop filter 0x285 0xc9 optimal serdes pll loop filter 0x286 0x0e optimal serdes pll loop filter 0x287 0x12 optimal serdes pll charge pump 0x28a 0x7b optimal serdes pll vco ldo 0x28b 0x00 optimal serdes pll configuration 0x290 0x89 optimal serdes pll vco varactor 0x294 0x24 optimal serdes pll charge pump 0x296 0x03 optimal serdes pll vco 0x297 0x0d optimal serdes pll vco 0x299 0x02 optimal serdes pll configuration 0x29a 0x8e optimal serdes pll vco varactor 0x29c 0x2a optimal serdes pll charge pump 0x29f 0x78 optimal serdes pll vco varactor 0x2a0 0x06 optimal serdes pll vco varactor 0x280 0x01 enable serdes pll 2 0x268 0x [7:6] eqmode see the equalization mode setup section [5:0] 0x22 required value (default) 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the correct register value. 2 verify that register 0x281[0] reads ba ck 1 after enabling the serdes pll to indicate that the serdes pll has locked. step 5: data link layer this section describes how to set up the data link layer of the serdes interface. this section deals with sysref processing, setting deterministic latency, and establishing the link. table 21. data link layer settings addr. bit no. value 1 variable description 0x301 0x subclass see the jesd204b setup section. 0x304 0x lmfcdel see the link latency setup section. 0x305 0x lmfcdel see the link latency section. 0x306 0x lmfcvar see the link latency setup section. 0x307 0x lmfcvar see the link latency setup section. 0x03a 0x01 set sync mode = one-shot sync; see the syncing lmfc signals section for other sync options. 0x03a 0x81 enable the sync machine. 0x03a 0xc1 arm the sync machine. sysref signal if subclass = 1, ensure that at least one sysref edge is sent to the device. 2 0x308 to 0x30b 0x xbarvals if remapping lanes, set up crossbar; see the crossbar setup section. 0x334 0x invlanes invert polarity of desired logical lanes. bit x of invlanes must be a 1 for each logical lane x to invert. 0x300 0x enable the links. 6 checksummode see the jesd204b setup section. 3 duallink 2 currentlink set to 0 to access link 0 status or 1 for link 1 status readbacks. see the jesd204b setup section. [1:0] enlinks enlinks = 3 if duallink = 1 (enables link 0 and link 1); enlinks = 1 if duallink = 0 (enables link 0 only). 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the correct register value. 2 verify that register 0x03b[3] reads back 1 after sending at least one sysref edge to the device to indicate that the lmfc sync machine has properly locked.
ad9144 data sheet rev. a | page 28 of 125 step 6: optional error monitoring for jesd204b error monitoring, see the jesd204b error monitoring section. for other error checks, see the interrupt request operation section. step 7: optional features there are a number of optional features that can be enabled. table 22 provides links to the sections describing each feature. these features can be enabled during the digital datapath configuration step or after the link is set up, because it is not required to configure them for the link to be established, unlike interpolation. unless otherwise noted, these features are paged as described in the dual paging section. paging is particularly important for dual specific settings like digital gain, phase adjust, and dc offset. table 22. optional features feature default description digital modulation off modulates the data with a desired carrier. see the digital modulation section. inverse sinc on improves pass-band flatness. see the inverse sinc section. digital gain 2.7 db multiplies data by a factor. can compensate inverse sinc usage or balance i/q amplitude. see the digital gain section. phase adjust off used to balance i/q phase. see the phase adjust section. dc offset off used to cancel lo leakage. see the dc offset section. group delay 0 used to control overall latency. see the group delay section. downstream protection off used to protect downstream components. see the downstream protection section. self calibration off used to improve dac linearity. not paged by the dual paging register. see the self calibration section.
data sheet ad9144 rev. a | page 29 of 125 dac pll setup this section explains how to select the appropriate lodivmode, refdivmode, and bcount in the step 1: start up the dac section. these parameters depend on the desired dac clock frequency (f dacclk ) and dac reference clock frequency (f ref ). when using the dac pll, the reference clock signal is applied to the clk differential pins (pin 2 and pin 3). table 23. dac pll lodivmode settings dac frequency range (mhz) lodivmode, register 0x08b[1:0] 1500 to 2800 1 750 to 1500 2 420 to 750 3 table 24. dac pll refdivmode settings dac pll reference frequency (f ref ) (mhz) divide by (refdivfactor) refdivmode, register 0x08c[2:0] 35 to 80 1 0 80 to 160 2 1 160 to 320 4 2 320 to 640 8 3 640 to 1000 16 4 the vco frequency (f vco ) is related to the dac clock frequency according to the following equation: f vco = f dacclk 2 lodivmode + 1 where 6 ghz ? f vco ? 12 ghz. bcount must be between 6 and 127 and is calculated based on f dacclk and f ref as follows: bcount = floor(( f dacclk )/(2 f ref / refdivfactor )) where refdivfactor = 2 refdivmode (see table 24). finally, to finish configuring the dac pll, set the vco control registers up as described in table 25 based on the vco frequency (f vco ). write the registers listed in the table with the corresponding lookupvals. table 25. vco control lookup table reference vco frequency range (ghz) register 0x1b5 setting register 0x1bb setting register 0x1c5 setting f vco < 6.3 0x08 0x03 0x07 6.3 f vco < 7.25 0x09 0x03 0x06 f vco 7.25 0x09 0x13 0x06 for more information on the dac pll, see the dac input clock configurations section. interpolation the transmit path can use zero to three cascaded interpolation filters, which each provides a 2 increase in output data rate and a low-pass function. table 26 shows the different interpolation modes and the respective usable bandwidth along with the maximum f data rate attainable. table 26. interpolation modes and their usable bandwidth interpolation mode interpmode usable bandwidth max f data (mhz) 1 (bypass) 0x00 0.5 f data 1060 (serdes limited) 2 0x01 0.4 f data 1060 (serdes limited) 4 0x03 0.4 f data 700 8 0x04 0.4 f data 350 the usable bandwidth is defined for 1, 2, 4, and 8 modes as the frequency band over which the filters have a pass-band ripple of less than 0.001 db and an image rejection of greater than 85 db. for more information, see the interpolation filters section. jesd204b setup this section explains how to select a jesd204b operating mode for a desired application. this section defines appropriate values for checksummode, unusedlanes, duallink, currentlink, scrambling, l, f, k, m, n, np, subclass, s, hd, lane0checksum, and lanes needed for the step 3: transport layer section. note that duallink, scrambling, l, f, k, m, n, np, s, hd, and subclass must be set the same on the transmit side. for a summary of how a jesd204b system works and what each parameter means, see the jesd204b serial data interface section. available operating modes table 27. jesd204b operating modes (single-link only) mode parameter 0 1 2 3 m (converter count) 4 4 4 4 l (lane count) 8 8 4 2 s ((samples per converter) per frame) 1 2 1 1 f ((octets per frame) per lane) 1 2 2 4 table 28. jesd204b operating modes (single- or dual-link) mode parameter 4 5 6 7 9 10 m (converter count) 2 2 2 2 1 1 l (lane count) 4 4 2 1 2 1 s ((samples per converter) per frame) 1 2 1 1 1 1 f ((octets per frame) per lane) 1 2 2 4 1 2
ad9144 data sheet rev. a | page 30 of 125 for a particular application, the number of converters to use (m) and the f data (datarate) are known. the lanerate and number of lanes (l) can be traded off as follows: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l where lanerate is between 1.44 gbps and 10.64 gbps. octets per frame per lane (f) and samples per convertor per frame (s) define how the data is packed. if f = 1, the high density setting must be set to one (hd = 1). otherwise, set hd = 0. converter resolution and bits per sample (n and np) must both be set to 16. frames per multiframe (k) must be set to 32 for mode 0, mode 4 and mode 9. other modes can use either k = 16 or k = 32. duallink duallink sets up two independent jesd204b links, which allows each link to be reset independently. if this functionality is desired, set duallink to 1; if a single link is desired, set duallink to 0. note that link 0 and link 1 must have identical parameters. the operating modes available when using dual-link mode are shown in table 28. in addition to these operating modes, the modes in table 28 can also be used when using single-link mode. scrambling scrambling is a feature that makes the spectrum of the link data independent. this avoids spectral peaking and provides some protection against data dependent errors caused by frequency selective effects in the electrical interface. set to 1 if scrambling is being used, or to 0 if it is not. subclass subclass determines whether the latency of the device is deterministic, meaning it requires an external synchronization signal. see the subclass setup section for more information. currentlink set currentlink to either 0 or 1 depending on whether link 0 or link 1, respectively, needs to be configured. lanes lanes is used to enable and deskew particular lanes in two thermometer coded registers. lanes = (2 l ) ? 1. unusedlanes unusedlanes is used to turn off unused circuit blocks to save power. each physical lane that is not being used (serdinx) must be powered off by writing a 1 to the corresponding bit of register 0x201. for example, if using mode 6 in dual-link mode and sending data on serdin0, serdin1, serdin4, and serdin5, set unusedlanes = 0xcc to power off physical lane 2, lane 3, lane 6, and lane 7. checksummode checksummode must match the checksum mode used on the transmit side. if the checksum used is the sum of fields in the link configuration table, checksummode = 0. if summing the registers containing the packed link configuration fields, checksummode = 1. for more information on the how to calculate the two checksum modes, see the lane0checksum section. lane0checksum lane0checksum can be used for error checking purposes to ensure that the transmitter is set up as expected. both checksummode calculations use the fields contained in register 0x450 to register 0x45a. select whether to sum by fields or by registers, matching the setting on the transmitter. if checksummode = 0, the summation is computed by fields. the checksum is the lower 8 bits of the sum of the did, adjcnt, bid, adjdir, phadj, lid, scrambling, l C 1, f ? 1, k ? 1, m ? 1, cs, n ? 1, subclass, np ? 1, jesdver, s ? 1, hd, and cf variables. if checksummode = 1, the summation is computed by registers. the checksum is the sum of register 0x450 to register 0x45a, modulo 256. dac power-down setup as described in the step 1: start up the dac section, pddacs must be set to 0 if all 4 converters are being used. if fewer than four converters are being used, the unused converters must be powered down. table 29 can be used to determine which dacs are powered down based on the number of converters per link (m) and whether the device is in duallink mode. table 29. dac power-down configuration settings m (converters per link) duallink dacs to power down pddacs 0 1 2 3 1 0 0 1 1 1 0b0111 1 1 0 1 0 1 0b0101 2 0 0 0 1 1 0b0011 2 1 0 0 0 0 0b0000 4 0 0 0 0 0 0b0000 pdclocks if both dacs in dac dual b (dac2 and dac3) are powered down, the clock for dac dual b can be powered down. in this case, pdclocks = 0x40; if not, pdclocks = 0x00.
data sheet ad9144 rev. a | page 31 of 125 serdes clocks setup this section describes how to select the appropriate halfrate, ovsmp, and plldiv settings in the step 4: physical layer section. these parameters depend solely on the lane rate (the lane rate is established in the jesd204b setup section). table 30. serdes lane rate configuration settings lane rate (gbps) halfrate ovsmp plldiv 1.44 to 2.76 0 1 2 2.88 to 5.52 0 0 1 5.75 to 10.64 1 0 0 halfrate and ovsmp set how the clock detect and recover (cdr) circuit sample. see the serdes pll section for an explanation of how that circuit blocks works and the role of plldiv in the block. equalization mode setup set eqmode = 1 for a low power setting. select this mode if the insertion loss in the printed circuit board (pcb) is less than 12 db. for insertion losses greater than 12 db, but less than 17.5 db, set eqmode = 0. more details can be found in the equalization section. link latency setup this section describes the steps necessary to guarantee multichip deterministic latency in subclass 1 and to guarantee synchronization of links within a device in subclass 0. use this section to fill in lmfcdel, lmfcvar, and subclass in the step 5: data link layer section. for more information, see the syncing lmfc signals section. subclass setup the ad9144 supports jesd204b subclass 0 and subclass 1 operation. subclass 1 this mode gives deterministic latency and allows links to be synced to within ? dac clock periods. it requires an external sysref signal that is accurately phase aligned to the dac clock. subclass 0 this mode does not require any signal on the sysref pins (the pins can be left disconnected). subclass 0 still requires that all lanes arrive within the same lmfc cycle and that the dual dacs must be synchronized to each other (they are synchronized to an internal clock instead of to the sysref signal). set subclass to 0 or 1 as desired. link delay setup lmfcvar and lmfcdel are used to impose delays such that all lanes in a system arrive in the same lmfc cycle. the unit used internally for delays is the period of the internal processing clock (pclock), whose rate is 1/40 th the lane rate. delays that are not in pclock cycles must be converted before they are used. some useful internal relationships are defined as follows: pclockperiod = 40/lanerate the pclockperiod can be used to convert from time to pclock cycles when needed. pclockfactor = 4/ f (frames per pclock) the pclockfactor is used to convert from units of pclock cycles to frame clock cycles, which is needed to set lmfcdel in subclass 1. pclockspermf = k / pclockfactor (pclocks per lmfc cycle) where pclockspermf is the number or pclock cycles in a multiframe cycle. the values for pclockfactor and pclockpermf are given per jesd mode in table 31 and table 32. table 31. pclockfactor and pclockpermf per lmfc jesd mode id 0 1 2 3 pclockfactor 4 2 2 1 pclockpermf (k = 32) 8 16 16 32 pclockpermf (k = 16) n/a 1 8 8 16 1 n/a means not applicable. table 32. pclockfactor and pclockpermf per lmfc jesd mode id 4 5 6 7 9 10 pclockfactor 4 2 2 1 4 2 pclockpermf (k = 32) 8 16 16 32 8 16 pclockpermf (k = 16) n/a 1 8 8 16 n/a 1 8 1 n/a means not applicable. with known delays with information about all the system delays, lmfcvar and lmfcdel can be calculated directly. rxfixed (the fixed receiver delay in pclock cycles) and rxvar (the variable receiver delay in pclock cycles) can be found in table 8. txfixed (the fixed transmitter delay in pclock cycles) and txvar (the variable receiver delay in pclock cycles) can be found in the data sheet of the transmitter used. pcbfixed (the fixed pcb trace delay in pclock cycles) can be extracted from software; because this is generally much smaller than a pclock cycle, it can also be omitted. for both the pcb and transmitter delays, convert the delays into pclock cycles. for each lane mindelaylane = floor( rxfixed + txfixed + pcbfixed ) maxdelaylane = ceiling( rxfixed + rxvar + txfixed + txvar + pcbfixed )) where: mindelay is the minimum of all mindelaylane values across lanes, links, and devices. maxdelay is the maximum of all maxdelaylane values across lanes, links, and devices.
ad9144 data sheet rev. a | page 32 of 125 for safety, add a guard band of 1 pclock cycle to each end of the link delay as in the following equations: lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) note that if lmfcvar must be more than 10, the ad9144 is unable to tolerate the variable delay in the system. for subclass 1 lmfcdel = (( mindelay ? 1) pclockfactor ) % k for subclass 0 lmfcdel = ( mindelay ? 1) % pclockpermf program the same lmfcdel and lmfcvar across all links and devices. see the link delay setup example, with known delays section for an example calculation. without known delays if comprehensive delay information is not available or known, the ad9144 can read back the link latency between the lmfc rx and the last arriving lmfc boundary in pclock cycles. this information is then used to calculate lmfcvar and lmfcdel. for each link (on each device) 1. power up the board. 2. follow the steps in table 15 through table 21 of the device setup guide. 3. set the subclass and perform a sync. for one-shot sync, perform the writes in table 33. see the syncing lmfc signals section for alternate sync modes. 4. record dyn_link_latency_0 (register 0x302) as a value of delay for that link and power cycle. 5. record dyn_link_latency_1 (register 0x303) as a value of delay for that link and power cycle the system. repeat step 1 to step 5 twenty times for each device in the system. keep a single list of the delay values across all runs and devices. table 33. register configuration and procedure for one- shot sync addr. bit. no. value 1 variable description 0x301 0x subclass set subclass 0x03a 0x01 set sync mode to one-shot sync 0x03a 0x81 enable the sync machine 0x03a 0xc1 arm the sync machine sysref signal if subclass = 1, ensure that at least one sysref edge is sent to the device. 0x300 0x enable the links 6 checksummode see the jesd204b setup section 3 duallink see the jesd204b setup section 2 currentlink set to 0 to access link 0 status or 1 for link 1 status readbacks. see the jesd204b setup section. [1:0] enlinks enlinks = 3 if in duallink mode to enable link 0 and link 1; enlinks = 1 if not in duallink mode to enable link 0 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on se lecting the appropriate register value. the list of delay values is used to calculate lmfcdel and lmfcvar; however, first some of the delay values may need to be remapped. the maximum possible value for dyn_link_latency_x is one less than the number of pclocks in a multiframe (pclockspermf ) . it is possible that a rollover condition may be encountered, meaning the set of recorded delay values might roll over the edge of a multiframe. if so, delay values may be near both 0 and pclockspermf. if this occurs, add pclockspermf to the set of values near 0. for example, for delay value readbacks of 6, 7, 0, and 1, the 0 and 1 delay values must be remapped to 8 and 9, making the new set of delay values 6, 7, 8, and 9.
data sheet ad9144 rev. a | page 33 of 125 across power cycles, links, and devices ? mindelay is the minimum of all delay measurements ? maxdelay is the maximum of all delay measurements for safety, a guard band of 1 pclock cycle is added to each end of the link delay and calculate lmfcvar and lmfcdel with the following equation: lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) note that if lmfcvar must be more than 10, the ad9144 is unable to tolerate the variable delay in the system. for subclass 1 lmfcdel = (( mindelay ? 1) pclockfactor ) % k for subclass 0 lmfcdel = ( mindelay ? 1) % pclockpermf program the same lmfcdel and lmfcvar across all links and devices. see the link delay setup example, without known delay section for an example calculation. crossbar setup register 0x308 to register 0x30b allow arbitrary mapping of physical lanes (serdinx) to logical lanes used by the serdes deframers. table 34. crossbar registers address bits logical lane 0x308 [2:0] logical_lane0_src 0x308 [5:3] logical_lane1_src 0x309 [2:0] logical_lane2_src 0x309 [5:3] logical_lane3_src 0x30a [2:0] logical_lane4_src 0x30a [5:3] logical_lane5_src 0x30b [2:0] logical_lane6_src 0x30b [5:3] logical_lane7_src write each logical_laney_src with the number (x) of the desired physical lane (serdinx) from which to obtain data. by default, all logical lanes use the corresponding physical lane as their data source. for example, by default logical_lane0_ src = 0, meaning that logical lane 0 receives data from physical lane 0 (serdin0). if instead the user wants to use serdin4 as the source for logical lane 0, the user must write logical_lane0_src = 4.
ad9144 data sheet rev. a | page 34 of 125 jesd204b serial data interface jesd204b overview the ad9144 has eight jesd204b data ports that receive data. the eight jesd204b ports can be configured as part of a single jesd204b link or as part of two separate jesd204b links (dual- link mode) that share a single system reference (sysref) and device clock (clk). the jesd204b serial interface hardware consists of three layers: the physical layer, the data link layer, and the transport layer. these sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. figure 35 shows the communication layers implemented in the ad9144 serial data interface to recover the clock and deserialize, descramble, and deframe the data before it is sent to the digital signal processing section of the device. the physical layer is responsible for establishing a reliable channel between the transmitter and the receiver, the data link layer is responsible for unpacking the data into octets and descrambling the data, and the transport layer receives the descrambled jesd204b frames and converts them to dac samples. there are a number of jesd204b parameters (l, f, k, m, n, np, s, hd, and scrambling) that define how the data is packed and tell the device how to turn the serial data into samples. these parameters are defined in detail in the transport layer section. only certain combinations of parameters are supported. each supported combination is called a mode. in total, there are 10 single-link modes supported by the ad9144 , as described in table 35. in dual-link mode, there are six supported modes, as described in table 36. each of these tables shows the associated clock rates when the lane rate is 10 gbps. for a particular application, the number of converters to use (m) and the datarate are known. the lanerate and number of lanes (l) can be traded off as follows: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l where lanerate must be between 1.44 gbps and 10.64 gbps. achieving and recovering synchronization of the lanes is very important. to simplify the interface to the transmitter, the ad9144 designates a master synchronization signal for each jesd204b link. in single-link mode, syncout0 is used as the master signal for all lanes; in dual-link mode, syncout0 is used as the master signal for link 0, and syncout1 is used as the master signal for link 1. if any lane in a link loses synchronization, a resynchronization request is sent to the transmitter via the synchronization signal of the link. the transmitter stops sending data and instead sends synchronization characters to all lanes in that link until resynchronization is achieved. deserializer data link layer transport layer serdin0 sysref serdin7 dual a i data[15:0] dual a q data[15:0] dual b q data[15:0] dual b i data[15:0] to dac syncout1 syncout0 physical layer deserializer frame to samples qbd/ descrambler 11675-004 figure 35. functional block diagram of serial link receiver table 35. single-link jesd204b operating modes mode parameter 0 1 2 3 4 5 6 7 9 10 m (converter counts) 4 4 4 4 2 2 2 2 1 1 l (lane counts) 8 8 4 2 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 2 1 1 1 1 f (octets per frame per lane) 1 2 2 4 1 2 2 4 1 2 example clocks for 10 gbps lane rate pclock (mhz) 250 250 250 250 250 250 250 250 250 250 frame clock (mhz) 1000 500 500 250 1000 500 500 250 1000 500 sample clock (mhz) 1000 1000 500 250 1000 1000 500 250 1000 500
data sheet ad9144 rev. a | page 35 of 125 table 36. dual-link jesd204b operating modes for link 0 and link 1 mode parameter 4 5 6 7 9 10 m (converter counts) 2 2 2 2 1 1 l (lane counts) 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 1 f (octets/frame per lane) 1 2 2 4 1 2 example clock for 10 gbps lane rate pclock (mhz) 250 250 250 250 250 250 frame clock (mhz) 1000 500 500 250 1000 500 sample clock (mhz) 1000 1000 500 250 1000 500 physical layer the physical layer of the jesd204b interface, hereafter referred to as the deserializer, has eight identical channels. each channel consists of the terminators, an equalizer, a clock and data recovery (cdr) circuit, and the 1:40 demux function (see figure 36). equalizer cdr 1:40 deserializer from serdes pll spi c ontrol termination serdinx 11675-006 figure 36. deserializer block diagram jesd204b data is input to the ad9144 via the serdinx 1.2 v differential input pins as per the jesd204b specification. interface power-up and input termination before using the jesd204b interface, it must be powered up by setting register 0x200[0] = 0. in addition, each physical lane that is not being used (serdinx) must be powered down. to do so, set the corresponding bit x for physical lane x in register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. the ad9144 autocalibrates the input termination to 50 . before running the termination calibration, register 0x2aa, register 0x2ab, register 0x2b1, and register 0x2b2 must be written as described in table 37 to guarantee proper calibration. the termination calibration begins when register 0x2a7[0] and register 0x2ae[0] transition from low to high. register 0x2a7 controls autocalibration for phy 0, phy 1, phy 6, and phy 7. register 0x2ae controls autocalibration for phy 2, phy 3, phy 4, and phy 5. the phy termination autocalibration routine is as shown in table 37. table 37. phy termination autocalibration routine address value description 0x2aa 0xb7 serdes interface termination configuration 0x2ab 0x87 serdes interface termination configuration 0x2b1 0xb7 serdes interface termination configuration 0x2b2 0x87 serdes interface termination configuration 0x2a7 0x01 autotune phy terminations 0x2ae 0x01 autotune phy terminations the input termination voltage of the dac is sourced externally via the v tt pins (pin 21, pin 23, pin 40, and pin 43). set v tt by connecting it to svdd12. it is recommended that the jesd204b inputs be ac-coupled to the jesd204b transmit device using 100 nf capacitors. receiver eye mask the ad9144 complies with the jesd204b specification regarding the receiver eye mask and is capable of capturing data that complies with this mask. figure 37 shows the receiver eye mask normalized to the data rate interval with a 600 mv v tt swing. see the jesd204b specification for more information regarding the eye mask and permitted receiver eye opening. 525 55 0 ?55 ?525 amplitude (mv) 0 0.5 1.00 0.35 0.65 time (ui) lv-oif-11g-sr receiver eye mask 11675-007 figure 37. receiver eye mask
ad9144 data sheet rev. a | page 36 of 125 clock relationships the following clocks rates are used throughout the rest of the jesd204b section. the relationship between any of the clocks can be derived from the following equations: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l byterate = lanerate /10 this comes from 8-bit/10-bit encoding, where each byte is represented by 10 bits. pclockrate = byterate /4 the processing clock is used for a quad-byte decoder. framerate = byterate / f where f is defined as (bytes per frame) per lane. pclockfactor = framerate / pclockrate = 4/ f where: m is the jesd204b parameter for converters per link. l is the jesd204b parameter for lanes per link. f is the jesd204b parameter for octets per frame per lane. serdes pll functional overview of the serdes pll the independent serdes pll uses integer-n techniques to achieve clock synthesis. the entire serdes pll is integrated on-chip, including the vco and the loop filter. the serdes pll vco operates over the range of 5.65 ghz to 11.04 ghz. in the serdes pll, a vco divider block divides the vco clock by 2 to generate a 2.825 ghz to 5.52 ghz quadrature clock for the deserializer cores. this clock is the input to the clock and data recovery block that is described in the clock and data recovery section. the reference clock to the serdes pll is always running at a frequency, f ref = 1/40 of the lane rate = pclockrate. this clock is divided by a divfactor to deliver a clock to the pfd block that is between 35 mhz and 80 mhz. table 38 includes the respective serdes_pll_div_mode register settings for each of the desired divfactor options available. table 38. serdes pll divider settings lanerate (gbps) divide by (divfactor) serdes_pll_div_mode, register 0x289[1:0] 1.44 to 2.76 1 2 2.88 to 5.52 2 1 5.75 to 10.64 4 0 register 0x280 controls the synthesizer enable and recalibration. to enable the serdes pll, first set the pll divider register according to table 38, then enable the serdes pll by writing register 0x280[0] to 1. confirm that the serdes pll is working by reading register 0x281. if register 0x281[0] = 1, the serdes pll has locked. if register 0x281[3] = 1, the serdes pll was successfully calibrated. if register 0x281[4] or register 0x281[5] are high, the pll hit the upper or lower end of its calibration band and must be recalibrated by writing 0 and then 1 to register 0x280[2]. serdes pll fixed register writes to optimize the serdes pll across all operating conditions, the register writes in table 39 are recommended. table 39. serdes pll fixed register writes register address register value description 0x284 0x62 optimal serdes pll loop filter 0x285 0xc9 optimal serdes pll loop filter 0x286 0x0e optimal serdes pll loop filter 0x287 0x12 optimal serdes pll charge pump 0x28a 0x7b optimal serdes pll vco ldo 0x28b 0x00 optimal serdes pll configuration 0x290 0x89 optimal serdes pll vco varactor 0x294 0x24 optimal serdes pll charge pump 0x296 0x03 optimal serdes pll vco 0x297 0x0d optimal serdes pll vco 0x299 0x02 optimal serdes pll configuration 0x29a 0x8e optimal serdes pll vco varactor 0x29c 0x2a optimal serdes pll charge pump 0x29f 0x78 optimal serdes pll vco varactor 0x2a0 0x06 optimal serdes pll vco varactor serdes pll irq serdes pll lock and lost signals are available as irq events. use register 0x01f[3:2] to enable these signals, and then use register 0x023[3:2] to read back their statuses and reset the irq signals. see the interrupt request operation section for more information.
data sheet ad9144 rev. a | page 37 of 125 lc vco 5.65ghz to 11.04ghz charge pump pfd 80mhz max up down f ref bit rate 40 3.2ma fo cal alc cal cal control bits r1 c1 r3 c2 c3 vco ldo 2 80 2.825ghz to 5.52ghz output iq divfactor (1, 2, 4) 11675-011 figure 38. serdes pll synthesizer bloc k diagram including vco divider block clock and data recovery the deserializer is equipped with a cdr circuit. instead of recovering the clock from the jesd204b serial lanes, the cdr recovers the clocks from the serdes pll. the 2.825 ghz to 5.52 ghz output from the serdes pll, shown in figure 38, is the input to the cdr. a cdr sampling mode must be selected to generate the lane rate clock inside the device. if the desired lane rate is greater than 5.65 ghz, half rate cdr operation must be used. if the desired lane rate is less than 5.65 ghz, disable half rate operation. if the lane rate is less than 2.825 ghz, disable half rate and enable 2 oversampling to recover the appropriate lane rate clock. table 40 gives a breakdown of cdr sampling settings that must be set dependent on the lanerate. table 40. cdr operating modes lanerate (gbps) enhalfrate, register 0x230[5] cdr_oversamp, register 0x230[1] 1.44 to 2.76 0 1 2.88 to 5.52 0 0 5.75 to 10.64 1 0 the cdr circuit synchronizes the phase used to sample the data on each serial lane independently. this independent phase adjustment per serial interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a pcb. after configuring the cdr circuit, reset it and then release the reset by writing 1 and then 0 to register 0x206[0]. power-down unused phys note that any unused and enabled lanes consume extra power unnecessarily. each lane that is not being used (serdinx) must be powered off by writing a 1 to the corresponding bit of phy_pd (register 0x201). equalization to compensate for signal integrity distortions for each phy channel due to pcb trace length and impedance, the ad9144 employs an easy to use, low power equalizer on each jesd204b channel. the ad9144 equalizers can compensate for insertion losses far greater than required by the jesd204b specification. the equalizers have two modes of operation that are determined by the eq_power_mode register setting in register 0x268[7:6]. in low power mode (register 0x268[7:6] = 2b01) and operating at the maximum lane rate of 10 gbps, the equalizer can compensate for up to 12 db of insertion loss. in normal mode (register 0x268[7:6] = 2b00), the equalizer can compensate for up to 17.5 db of insertion loss. this performance is shown in figure 39 as an overlay to the jesd204b specification for insertion loss. figure 39 shows the equalization performance at 10.0 gbps, near the maximum baud rate for the ad9144. figure 40 and figure 41 are provided as points of reference for hardware designers and show the insertion loss for various lengths of well laid out stripline and microstrip transmission lines. see the hardware considerations section for specific layout recommendations for the jesd204b channel. low power mode is recommended if the insertion loss of the jesd204b pcb channels is less than that of the most lossy supported channel for lower power mode (shown in figure 39). if the insertion loss is greater than that, but still less than that of the most lossy supported channel for normal mode (shown in figure 39), use normal mode. at 10 gbps operation, the eq in normal mode consumes about 4 mw more power per lane used than in low power eq mode. note that either mode can be used in conjunction with transmitter preemphasis to ensure functionality and/or to optimize for power.
ad9144 data sheet rev. a | page 38 of 125 11675-339 insertion loss (db) frequency (ghz) 0 2 4 6 8 10 12 14 16 18 20 22 24 5.0 7.5 2.5 ad9144 allowed channel loss (low power mode) jesd204b spec allowed channel loss example of jesd204b compliant channe l example of ad9144 compatible channel (low power mode) example of ad9144 compatible channel (normal mode) ad9144 allowed channel loss (normal mode) figure 39. insertion loss allowed ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 012345678910 a ttenu a tion (db) frequency (ghz) stripline = 6? stripline = 10? stripline = 15? stripline = 20? stripline = 25? stripline = 30? 11675-010 figure 40. insertion loss of 50 striplines on fr4 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 012 3 45678910 a ttenu a tion (db) frequency (ghz) 6? microstrip 10? microstrip 15? microstrip 20? microstrip 25? microstrip 30? microstrip 11675-011 figure 41. insertion loss of 50 microstrips on fr4 data link layer the data link layer of the ad9144 jesd204b interface accepts the deserialized data from the phys and deframes and descrambles them so that data octets are presented to the transport layer to be put into dac samples. figure 42 shows the link mode block diagrams for single-link and dual-link configurations and the interaction between the physical layer and logical layer. the logical lanes and dacs can only be configured in sequential order; for example in mode 10, when in single-link mode, the ad9144 only uses logical lane 0 and dac0, and in dual-link mode, only uses logical lane 0, logical lane 1 and dac0, dac1. see the mode configuration maps section for further details on each of the mode configurations supported. the architecture of the data link layer is shown in figure 43. the data link layer consists of a synchronization fifo for each lane, a crossbar switch, a deframer, and descrambler. the ad9144 can operate as a single-link or dual-link high speed jesd204b serial data interface. when operating in dual- link mode, configure both links with the same jesd204b parameters because they share a common device clock and system reference. all eight lanes of the jesd204b interface handle link layer communications such as code group synchronization, frame alignment, and frame synchronization. the ad9144 decodes 8-bit/10-bit control characters, allowing marking of the start and end of the frame and alignment between serial lanes. each ad9144 serial interface link can issue a synchronization request by setting its syncout0 / syncout1 signal low. the synchronization protocol follows section 4.9 of the jesd204b standard. when a stream of four consecutive /k/ symbols is received, the ad9144 deactivates the synchronization request by setting the syncout0 / syncout1 signal high at the next internal lmfc rising edge. then, it waits for the transmitter to issue an ilas. during the ilas sequence, all lanes are aligned using the /a/ to /r/ character transition as described in the jesd204b serial link establishment section. elastic buffers hold early arriving lane data until the alignment character of the latest lane arrives. at this point, the buffers for all lanes are released and all lanes are aligned (see figure 44).
data sheet ad9144 rev. a | page 39 of 125 serdin0/physical lane 0 serdin1/physical lane 1 serdin2/physical lane 2 serdin3/physical lane 3 serdin4/physical lane 4 serdin5/physical lane 5 serdin6/physical lane 6 serdin7/physical lane 7 logical lane 0/link 0 lane 0 logical lane 1/link 0 lane 1 logical lane 2/link 0 lane 2 logical lane 3/link 0 lane 3 logical lane 4/link 0 lane 4 logical lane 5/link 0 lane 5 logical lane 6/link 0 lane 6 logical lane 7/link 0 lane 7 physical lanes logical lanes dac0 dac1 dac2 dac3 quad-byte deframer (qbd0) single-link mode serdin0/physical lane 0 serdin1/physical lane 1 serdin2/physical lane 2 serdin3/physical lane 3 serdin4/physical lane 4 serdin5/physical lane 5 serdin6/physical lane 6 serdin7/physical lane 7 logical lane 0/link 0 lane 0 logical lane 1/link 0 lane 1 logical lane 2/link 0 lane 2 logical lane 3/link 0 lane 3 logical lane 4/link 1 lane 0 logical lane 5/link 1 lane 1 logical lane 6/link 1 lane 2 logical lane 7/link 1 lane 3 physical lanes logical lanes dac0 dac1 dac2 dac3 dual-link mode physical layer (phy) crossbar logical layer qbd dac core 11675-442 crossbar register 0x308 to register 0x30b crossbar register 0x308 to register 0x30b quad-byte deframer 0 (qbd0) quad-byte deframer 1 (qbd1) figure 42. link mode functional diagram lane 0 deserialized and descrambled data lane 0 data clock serdin0 fifo serdin7 fifo cross bar switch lane 7 deserialized and descrambled data lane 7 data clock pclk data link layer spi control sysref syncoutx descramble 10-bit/8-bit decode system clock phase detect lane0 octets lane7 octets quad-byte deframer qbd 11675-012 figure 43. data link layer block diagram
ad9144 data sheet rev. a | page 40 of 125 l receive lanes (latest arrival) l aligned receive lanes 0 character elastic buffer delay of latest arrival k = k28.5 code group synchronization comma character a = k28.3 lane alignment symbol f = k28.7 frame alignment symbol r = k28.0 start of multiframe q = k28.4 start of link configuration data c = jesd204b link configuration parameters d = dx.y data symbol 4 character elastic buffer delay of earliest arrival l receive lanes (earliest arrival) kkkkkkkrdd kkkrdd ddarqc c ddarqc c ddardd ddardd kkkkkkkrdd ddarqc c ddardd 11675-013 figure 44. lane alignment during ilas jesd204b serial link establishment a brief summary of the high speed serial link establishment process for subclass 1 is provided. see section 5.3.3 of the jesd204b specifications document for complete details. step 1: code group synchronization each receiver must locate k (k28.5) characters in its input data stream. after four consecutive k characters are detected on all link lanes, the receiver block deasserts the syncoutx signal to the transmitter block at the receiver local multiframe clock (lmfc) edge. the transmitter captures the change in the syncoutx signal, and at a future transmitter lmfc rising edge, starts the initial lane alignment sequence (ilas). step 2: initial lane alignment sequence the main purposes of this phase are to align all the lanes of the link and to verify the parameters of the link. before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. the ilas consists of four or more multiframes. the last character of each multiframe is a multiframe alignment character, /a/. the first, third, and fourth multiframes are populated with predetermined data values. note that section 8.2 of the jesd204b specifications document describes the data ramp that is expected during ilas. by default, the ad9144 does not require this ramp. register 0x47e[0] can be set high to require the data ramp. the deframer uses the final /a/ of each lane to align the ends of the multiframes within the receiver. the second multiframe contains an r (k28.0), q (k28.4), and then data corresponding to the link parameters. additional multiframes can be added to the ilas if needed by the receiver. by default, the ad9144 uses four multiframes in the ilas (this can be changed in register 0x478). if using subclass 1, exactly four multiframes must be used. after the last /a/ character of the last ilas, multiframe data begins streaming. the receiver adjusts the position of the /a/ character such that it aligns with the internal lmfc of the receiver at this point. step 3: data streaming in this phase, data is streamed from the transmitter block to the receiver block. optionally, data can be scrambled. scrambling does not start until the very first octet following the ilas. the receiver block processes and monitors the data it receives for errors, including: ? bad running disparity (8-bit/10-bit error) ? not in table (8-bit/10-bit error) ? unexpected control character ? bad ilas ? interlane skew error (through character replacement) if any of these errors exist, they are reported back to the transmitter in one of a few ways (see the jesd204b error monitoring section for details). ? syncoutx signal assertion: resynchronization ( syncoutx signal pulled low) is requested at each error for the last two errors. for the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold. ? for the first three errors, each multiframe with an error in it causes a small pulse on syncoutx . ? errors can optionally trigger an irq event, which can be sent to the transmitter. various test modes for verifying the link integrity can be found in the jesd204b test modes section.
data sheet ad9144 rev. a | page 41 of 125 lane fifo the fifos in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface with the deframer clock by adjusting the phase of the incoming data. the fifo absorbs timing variations between the data source and the deframer; this allows up to two pclock cycles of drift from the transmitter. the fifo_status_reg_0 register and fifo_status_reg_1 register (register 0x30c and register 0x30d, respectively) can be monitored to identify whether the fifos are full or empty. lane fifo irq an aggregate lane fifo error bit is also available as an irq event. use register 0x01f[1] to enable the fifo error bit, and then use register 0x023[1] to read back its status and reset the irq signal. see the interrupt request operation section for more information. crossbar switch register 0x308 to register 0x30b allow arbitrary mapping of physical lanes (serdinx) to logical lanes used by the serdes deframers. table 41. crossbar registers address bits logical lane 0x308 [2:0] logical_lane0_src 0x308 [5:3] logical_lane1_src 0x309 [2:0] logical_lane2_src 0x309 [5:3] logical_lane3_src 0x30a [2:0] logical_lane4_src 0x30a [5:3] logical_lane5_src 0x30b [2:0] logical_lane6_src 0x30b [5:3] logical_lane7_src write each logical_laney_src with the number (x) of the desired physical lane (serdinx) from which to obtain data. by default, all logical lanes use the corresponding physical lane as their data source. for example, by default logical_ lane0_src = 0; therefore, logical lane 0 obtains data from physical lane 0 (serdin0). if instead the user wants to use serdin4 as the source for logical lane 0, the user must write logical_lane0_src = 4. lane inversion register 0x334 allows inversion of desired logical lanes, which can be used to ease routing of the serdinx signals. for each logical lane x, set bit x of register 0x334 to 1 to invert it. deframers the ad9144 consists of two quad-byte deframers (qbds). each deframer takes in the 8-bit/10-bit encoded data from the deserializer (via the crossbar switch), decodes it, and descrambles it into jesd204b frames before passing it to the transport layer to be converted to dac samples. the deframer processes four symbols (or octets) per processing clock (pclock) cycle. in single-link mode, deframer 0 is used exclusively and deframer 1 remains inactive. in dual-link mode, both qbds are active and must be configured separately using the link_page bit (register 0x300[2]) to select whic h link is being configured. the link_mode bit (register 0x300[3]) is 1 for dual-link, or 0 for single-link. each deframer uses the jesd204b parameters that the user has programmed into the register map to identify how the data has been packed and how to unpack it. the jesd204b parameters are discussed in detail in the transport layer section; many of the parameters are also needed in the transport layer to convert jesd204b frames into samples. descrambler the ad9144 provides an optional descrambler block using a self synchronous descrambler with a polynomial: 1 + x 14 + x 15 . enabling data scrambling reduces spectral peaks that are produced when the same data octets repeat from frame to frame. it also makes the spectrum data independent so that possible frequency-selective effects on the electrical interface do not cause data-dependent errors. descrambling of the data is enabled by setting the scr bit (register 0x453[7]) to 1. syncing lmfc signals the first step in guaranteeing synchronization across links and devices begins with syncing the lmfc signals. each dac dual (dac dual a: dac0/dac1 and dac dual b: dac2/dac3) has its own lmfc signal. in subclass 0, the lmfc signals for each of the two links are synchronized to an internal processing clock. in subclass 1, all lmfc signals (for all duals and devices) are synchronized to an external sysref signal. all lmfc sync registers are paged as described in the dual paging section. sysref signal the sysref signal is a differential source synchronous input that synchronizes the lmfc signals in both the transmitter and receiver in a jesd204b subclass 1 system to achieve deterministic latency. the sysref signal is an active high signal that is sampled by the device clock rising edge. it is best practice that the device clock and sysref signals be generated by the same source, such as the ad9516-1 clock generator, so that the phase alignment between the signals is fixed. when designing for optimum deterministic latency operation, consider the timing distribution skew of the sysref signal in a multipoint link system (multichip). the ad9144 supports a single pulse or step, or a periodic sysref signal. the periodicity can be continuous, strobed, or gapped periodic. the sysref signal can always be dc-coupled (with a common-mode voltage of 0 v to 2 v). when dc-coupled, a small amount of common-mode current (<500 a) is drawn from the sysref pins. see figure 45 for the sysref internal circuit.
ad9144 data sheet rev. a | page 42 of 125 to avoid this common-mode current draw, a 50% duty-cycle periodic sysref signal can be used with ac coupling capacitors. if ac-coupled, the ac coupling capacitors combine with the resistors shown in figure 45 to make a high-pass filter with rc time constant = rc. select c such that > 4/sysref freq. in addition, the edge rate must be sufficiently fastat least 1.3 v/ns is recommended per table 5to meet the sysref vs. dac clock keep out window (kow) requirements. it is possible to use ac-coupled mode without meeting the frequency to time-constant constraint mentioned by using sysref hysteresis (register 0x081 and register 0x082). however, this increases the dac clock kow (table 5 does not apply) by an amount depending on sysref frequency, level of hysteresis, capacitor choice, and edge rate. 3k ? ~600mv 1.2 v sysref+ sysref? 3k ? 11675-015 figure 45. sysref input circuit sync processing modes overview the ad9144 supports various lmfc sync processing modes. these modes are one-shot, cont inuous, windowed continuous, and monitor modes. all sync processing modes perform a phase check to see that the lmfc is phase aligned to an alignment edge. in subclass 1, the sysref pulse acts as the alignment edge; in subclass 0, an internal processing clock acts as the alignment edge. if the signals are not in phase, a clock rotation occurs to align the signals. the sync modes are described in the following sections. see the sync procedure section for details on the procedure for syncing the lmfc signals. one-shot sync mode (syncmode = 0x1) in one-shot sync mode, a phase check occurs on only the first alignment edge that is received after the sync machine is armed. if the phase error is larger than a specified window error tolerance, a phase adjustment occurs. though an lmfc synchronization occurs only once, the sysref signal can still be continuous. continuous sync mode (syncmode = 0x2) continuous mode must only be used in subclass 1 with a periodic sysref signal. in continuous mode, a phase check/alignment occurs on every alignment edge. continuous mode differs from one-shot mode in two ways. first, no spi cycle is required to arm the device; the alignment edge seen after continuous mode is enabled results in a phase check. second, a phase check (and when necessary, clock rotation) occurs on every alignment edge in continuous mode. the one caveat to the previous statement is that when a phase rotation cycle is underway, subsequent alignment edges are ignored until the logic lane is ready again. the maximum acceptable phase error (in dac clock cycles) between the alignment edge and the lmfc edge is set in the error window tolerance register. if continuous sync mode is used with a nonzero error window tolerance, a phase check occurs on every sysref pulse, but an alignment occurs only if the phase error is greater than the specified error window tolerance. if the jitter of the sysref signal violates the kow specification given in table 5 and therefore causes phase error uncertainty, the error tolerance can be increased to avoid constant clock rotations. note that this means the latency is less deterministic by the size of the window. if the error window tolerance must be set above 3, subclass 0 with a one-shot sync is recommended. for debug purposes, syncarm (register 0x03a[6]) can be used to inform the user that alignment edges are being received in continuous mode. because the syncarm bit is self cleared after an alignment edge is received, the user can arm the sync (syncarm (register 0x03a[6]) = 1), and then read back syncarm. if syncarm = 0, the alignment edges are being received and phase checks are occurring. arming the sync machine in this mode does not affect the operation of the device. one-shot then monitor sync mode (syncmode = 0x9) in one-shot then monitor mode, the user can monitor the phase error in real time. use this sync mode with a periodic sysref signal. a phase check and alignment occurs on the first alignment edge received after the sync machine is armed. on all subsequent alignment edges the phase is monitored and reported, but no clock phase adjustment occurs. the phase error can be monitored on the sync_currerr_l register (register 0x03c[3:0]). immediately after an alignment occurs, currerr = 0 indicates that there is no difference between the alignment edge and the lmfc edge. on every subsequent alignment edge, the phase is checked. if the alignment is lost, the phase error is reported in the sync_ currerr_l register in dac clock cycles. if the phase error is beyond the selected window tolerance (register 0x034[2:0]), one bit of register 0x03d[7:6] is set high depending on whether the phase error is on the low or high side. when an alignment occurs, snapshots of the last phase error (register 0x03c[3:0]) and the corresponding error flags (register 0x03d[7:6]) are placed into readable registers for reference (register 0x038 and register 0x039, respectively).
data sheet ad9144 rev. a | page 43 of 125 sync procedure the procedure for enabling the sync is as follows: 1. set register 0x008 to 0x03 to sync the lmfc for both duals (dac0/dac1 and dac2/dac3). 2. set the desired sync processing mode. the sync processing mode settings are listed in table 42. 3. for subclass 1, set the error window according to the uncertainty of the sysref signal relative to the dac clock and the tolerance of the application for deterministic latency uncertainty. sync window tolerance settings are given in table 43. 4. enable sync by writing syncenable (register 0x03a[7] = 1). 5. if in one-shot mode, arm the sync machine by writing syncarm (register 0x03a[6] = 1). 6. if in subclass 1, ensure that at least one sysref pulse is sent to the device. 7. check the status by reading the following bit fields: a) sync_busy (register 0x03b[7]) = 0 to indicate that the sync logic is no longer busy. b) sync_lock (register 0x03b[3]) = 1 to indicate that the signals are aligned. this bit updates on every phase check. c) sync_wlim (register 0x03b[1]) = 0 to indicate that the phase error is not beyond the specified error window. this bit updates on every phase check. d) sync_rotate (register 0x03b[2]) = 1 if the phases were not aligned before the sync and an alignment occurred; this indicates that a clock alignment occurred. this bit is sticky and can be cleared only by writing to the syncclrstky control bit (register 0x03a[5]). e) sync_trip (register 0x03b[0]) = 1 to indicate alignment edge received and phase check occurred. this bit is sticky and can be cleared only by writing to the syncclrstky control bit (register 0x03a[5]). table 42. sync processing modes sync processing mode syncmode (register 0x03a[3:0]) one-shot 0x01 continuous 0x02 one-shot then monitor 0x09 table 43. sync window tolerance sync error window tolerance errwindow (register 0x034[2:0]) ? dac clock cycles 0x00 1 dac clock cycles 0x01 2 dac clock cycles 0x02 3 dac clock cycles 0x03 lmfc sync irq the sync status bits (synclock, syncrotate, synctrip, and syncwlim) are available as irq events. use register 0x021[3:0] to enable the sync status bits for dac dual a (dac0 and dac1), and then use register 0x025[3:0] to read back their statuses and reset the irq signals. use register 0x022[3:0] to enable the sync status bits for dac dual b (dac2 and dac3), and then use register 0x026[3:0] read back their statuses and reset the irq signals. see the interrupt request operation section for more information. deterministic latency jesd204b systems contain various clock domains distributed throughout each system. data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the jesd204b link. these ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with each new link establishment. section 6 of the jesd204b specification addresses the issue of deterministic latency with mechanisms defined as subclass 1 and subclass 2. the ad9144 supports jesd204b subclass 0 and subclass 1 oper- ation, but not subclass 2. write the subclass to register 0x301[2:0] and once per link to register 0x458[7:5]. subclass 0 this mode does not require any signal on the sysref pins, which can be left disconnected. subclass 0 still requires that all lanes arrive within the same lmfc cycle, and the dual dacs must be synchronized to each other. minor subclass 0 caveats because the ad9144 requires an ilas, the nonmultiple converter single lane (nmcda-sl) case from the jesd204a specification is only supported when using the optional ilas. error reporting using syncoutx is not supported when using subclass 0 with f = 1. subclass 1 this mode gives deterministic latency and allows links to be synced to within ? of a dac clock period. it requires an external sysref signal that is accurately phase aligned to the dac clock.
ad9144 data sheet rev. a | page 44 of 125 deterministic latency requirements several key factors are required for achieving deterministic latency in a jesd204b subclass 1 system. ? sysref signal distribution skew within the system must be less than the desired uncertainty. ? sysref setup and hold time requirements must be met for each device in the system. ? the total latency variation across all lanes, links, and devices must be 10 pclock periods. this includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. link delay the link delay of a jesd204b system is the sum of fixed and variable delays from the transmitter, channel, and receiver as shown in figure 48. for proper functioning, all lanes on a link must be read during the same lmfc period. section 6.1 of the jesd204b specification states that the lmfc period must be larger than the maximum link delay. for the ad9144 , this is not necessarily the case; instead, the ad9144 uses a local lmfc for each link (lmfc rx ) that can be delayed from the sysref aligned lmfc. because the lmfc is periodic, this can account for any amount of fixed delay. as a result, the lmfc period must only be larger than the variation in the link delays, and the ad9144 can achieve proper performance with a smaller total latency. figure 46 and figure 47 show a case where the link delay is larger than an lmfc period. note that it can be accommodated by delaying lmfc rx . ilas data power cycle variance lmfc a ligned dat a early arriving lmfc reference late arriving lmfc reference 11675-018 figure 46. link delay > lmfc period example ilas data frame clock power cycle variance lmfc aligned data lmfc rx lmfc_delay lmfc reference for all power cycles 11675-019 figure 47. lmfc_delay to comp ensate for link delay > lmfc 11675-017 ilas ilas fixed delay variable delay power cycle variance data lmfc a ligned data at rx output data at tx input data dsp channel logic device (jesd204b tx) jesd204b rx dac link delay = delay fixed + delay variable figure 48. jesd204b link delay = fixed delay + variable delay
data sheet ad9144 rev. a | page 45 of 125 the method for setting the lmfcdel and lmfcvar is described in the link delay setup section. setting lmfcdel appropriately ensures that all the corresponding data samples arrive in the same lmfc period. then lmfcvar is written into the receive buffer delay (rbd) to absorb all link delay variation. this ensures that all data samples have arrived before reading. by setting these to fixed values across runs and devices, deterministic latency is achieved. the rbd described in the jesd204b specification takes values from 1 to k frame clock cycles, while the rbd of the ad9144 takes values from 0 to 10 pclock cycles. as a result, up to 10 pclock cycles of total delay variation can be absorbed. because lmfcvar is in pclock cycles and lmfcdel is in frame clock cycles, a conversion between these two units is needed. the pclockfactor, or number of frame clock cycles per pclock cycle, is equal to 4/f. for more information on this relationship, see the clock relationships section. two examples follow that show how to determine lmfcvar and lmfcdel. after they are calculated, write lmfcdel into both register 0x304 and register 0x305 for all devices in the system, and write lmfcvar to both register 0x306 and register 0x307 for all devices in the system. link delay setup example, with known delays all the known system delays can be used to calculate lmfcvar and lmfcdel, as described in the link delay setup section. the example shown in figure 49 is demonstrated in the following steps according to the procedure outlined in the link delay setup section. note that this example is in subclass 1 to achieve deterministic latency, which has a pclockfactor (4/f) of 2 frameclock cycles per pclock cycle, and uses k = 32 (frames/multiframe). because pcbfixed << pclockperiod, pcbfixed is negligible in this example and not included in the calculations. 1. find the receiver delays using table 8. rxfixed = 17 pclock cycles rxvar = 2 pclock cycles 2. find the transmitter delays. the equivalent table in the example jesd204b core (implemented on a gth or gtx transceiver on a virtex-6 fpga) states that the delay is 56 2 byte clock cycles. because the pclockrate = byterate/4, as described in the clock relationships section, the transmitter delays in pclock cycles are txfixed = 54/4 = 13.5 pclock cycles txvar = 4/4 = 1 pclock cycle 3. calculate mindelaylane as follows: mindelaylane = floor( rxfixed + txfixed + pcbfixed ) = floor(17 + 13.5 + 0) = floor(30.5) mindelaylane = 30 4. calculate maxdelaylane as follows: maxdelaylane = ceiling( rxfixed + rxvar + txfixed + txvar + pcbfixed )) = ceiling(17 + 2 + 13.5 + 1 + 0) = ceiling(33.5) maxdelaylane = 34 5. calculate lmfcvar as follows: lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) = (34 + 1) ? (30 ? 1) = 35 ? 29 lmfcvar = 6 pclock cycles 6. calculate lmfcdel as follows: lmfcdel = (( mindelay ? 1) pclockfactor ) % k = ((30 ? 1) 2) % 32 = (29 2) % 32 = 58 % 32 lmfcdel = 26 frame clock cycles 7. write lmfcdel to both register 0x304 and register 0x305 for all devices in the system. write lmfcvar to both register 0x306 and register 0x307 for all devices in the system. 11675-024 frame clock lmfc pclock data data at tx framer ilas lmfc rx total fixed latency = 30 pclock cycles lmfc delay = 26 frame clock cycles pcb fixed delay data aligned lane data at rx deframer output ilas total variable latency = 4 pclock cycles tx var delay rx var delay figure 49. lmfc_delay calculation example
ad9144 data sheet rev. a | page 46 of 125 link delay setup example, without known delay if the system delays are not known, the ad9144 can read back the link latency between lmfc rx for each link and the sysref aligned lmfc. this information is then used to calculate lmfcvar and lmfcdel, as shown in the without known delays section. figure 51 shows how dyn_link_latency_x (register 0x302 and register 0x303) provides a readback showing the delay (in pclock cycles) between lmfc rx and the transition from ilas to the first data sample. by repeatedly power-cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate lmfcvar and lmfcdel. the example shown in figure 51 is demonstrated in the following steps according to the procedure outlined in the without known delays section. note that this example is in subclass 1 to achieve deterministic latency, which has a pclockfactor (frameclockrate/ pclockrate) of 2 and uses k = 16; therefore pclockspermf = 8. 1. in figure 51, for link a, link b, and link c, the system containing the ad9144 (including the transmitter) is power cycled and configured 20 times. the ad9144 is configured as described in the device setup guide. because the point of this exercise is to determine lmfcdel and lmfcvar, the lmfcdel is programmed to 0 and the dyn_ link_latency_x is read from register 0x302 and register 0x303 for link 0 and link 1, respectively. the variation in the link latency over the 20 runs is shown in figure 51 in grey. ? link a gives readbacks of 6, 7, 0, and 1. note that the set of recorded delay values rolls over the edge of a multiframe at the boundary k/pclockfactor = 8. add pclockspermf = 8 to low set. delay values range from 6 to 9. ? link b gives delay values from 5 to 7. ? link c gives delay values from 4 to 7. 2. calculate the minimum of all delay measurements across all power cycles, links, and devices: mindelay = min(all delay values) = 4 3. calculate the maximum of all delay measurements across all power cycles, links, and devices: maxdelay = max(all delay values) = 9 4. calculate the total delay variation (with guard band) across all power cycles, links, and devices: lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) = (9 + 1) ? (4 ? 1) = 10 ? 3 = 7 pclock cycles 5. calculate the minimum delay in frame clock cycles (with guard band) across all power cycles, links, and devices: lmfcdel = (( mindelay ? 1) pclockfactor ) % k = ((4 ? 1) 2) % 16 = (3 2) % 16 = 6 % 16 = 6 frame clock cycles 6. write lmfcdel to both register 0x304 and register 0x305 for all devices in the system. write lmfcvar to both register 0x306 and register 0x307 for all devices in the system. ilas data sysref aligned data lmfc rx dyn_link_latency 11675-022 figure 50. dyn_link_latency illustration 0123456701234567 dyn_link_latency_cnt aligned data (link a) deterministically delayed data lmfc rx aligned data (link b) aligned data (link c) frame clock lmfc pclock data ilas data ilas data ilas data ilas lmfc_delay = 6 (frame clock cycles) lmfc_var = 7 (pclock cycles) 11675-025 figure 51. multilink synchronization settings, derived method example
data sheet ad9144 rev. a | page 47 of 125 transport layer delay buffer 1 delay buffer 0 f2s_0 f2s_1 dac a_i0[15:0] dac a_q0[15:0] pclk_1 lane 0 octets lane 7 octets pclk_0 spi control lane 3 octets lane 4 octets dac b_i0[15:0] dac b_q0[15:0] transport layer (qbd) spi control 11675-026 figure 52. transport layer block diagram the transport layer receives the descrambled jesd204b frames and converts them to dac samples based on the programmed jesd204b parameters shown in table 44. a number of device parameters are defined in table 45. table 44. jesd204b transport layer parameters parameter description f number of octets per frame per lane: 1, 2, or 4. k number of frames per multiframe. k = 32 if f = 1, k = 16 or 32 otherwise. l number of lanes per converter device (per link), as follows: 1, 2, 4, or 8 (single-link mode). 1, 2, or 4 (dual-link mode). m number of converters per device (per link), as follows: 1, 2, or 4 (single-link mode). 1 or 2 (dual-link mode). s number of samples per conv erter, per frame: 1 or 2. table 45. jesd204b device parameters parameter description cf number of control words per device clock per link. not supported, must be 0. cs number of control bits per conversion sample. not supported, must be 0. hd high density user data fo rmat. used when samples must be split across lanes. set to 1 when f = 1, otherwise 0. n converter resolution = 16. n ? (np) total number of bits per sample = 16. certain combinations of these parameters, called jesd204b operating modes, are supported by the ad9144 . see table 46 and table 47 for a list of supported modes, along with their associated clock relationships.
ad9144 data sheet rev. a | page 48 of 125 table 46. single-link jesd204b operating modes mode parameter 0 1 2 3 4 5 6 7 9 10 m (converter count) 4 4 4 4 2 2 2 2 1 1 l (lane count) 8 8 4 2 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 2 1 1 1 1 f (octets per frame, per lane) 1 2 2 4 1 2 2 4 1 2 k 1 (frames per multiframe) 32 16/ 32 16/32 16/32 32 16/32 16/32 16/32 32 16/32 hd (high density) 1 0 0 0 1 0 0 0 1 0 n (converter resolution) 16 16 16 16 16 16 16 16 16 16 np (bits per sample) 16 16 16 16 16 16 16 16 16 16 example clocks for 10 gbps lane rate pclock rate (mhz) 250 250 250 250 250 250 250 250 250 250 frame clock rate (mhz) 1000 500 500 250 1000 500 500 250 1000 500 data rate (mhz) 1000 1000 500 250 1000 1000 500 250 1000 500 1 k must be 32 in mode 0, mode 4, and mode 9. k can be 16 or 32 in all other modes. table 47. dual-link jesd204b operating modes for link 0 and link 1 mode parameter 4 5 6 7 9 10 m (converter count) 2 2 2 2 1 1 l (lane count) 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 1 f (octets per frame per lane) 1 2 2 4 1 2 k 1 (frames per multiframe) 32 16/32 16/32 16/32 32 16/32 hd (high density) 1 0 0 0 1 0 n (converter resolution) 16 16 16 16 16 16 np (bits per sample) 16 16 16 16 16 16 example clocks for 10 gbps lane rate pclock rate (mhz) 250 250 250 250 250 250 frame clock rate (mhz) 1000 500 500 250 1000 500 data rate (mhz) 1000 1000 500 250 1000 500 1 k must be 32 in mode 4 and mode 9. k can be 16 or 32 in all other modes.
data sheet ad9144 rev. a | page 49 of 125 configuration parameters the ad9144 modes refer to the link configuration parameters for l, k, m, n, np, s, and f. table 48 provides the description and addresses for these settings. table 48. configuration parameters jesd204b setting description address l ? 1 number of lanes ? 1. 0x453[4:0] f ? 1 number of ((octets per frame) per lane) ? 1. 0x454[7:0] k ? 1 number of frames per multiframe ? 1. 0x455[4:0] m ? 1 number of converters ? 1. 0x456[7:0] n ? 1 converter bit resolution ? 1. 0x457[4:0] np ? 1 bit packing per sample ? 1. 0x458[4:0] s ? 1 number of ((samples per converter) per frame) ? 1. 0x459[4:0] hd high density format. set to 1 if f = 1. leave at 0 if f 1. 0x45a[7] f 1 f parameter, in ((octets per frame) per lane). 0x476[7:0] did device id. match the device id sent by the transmitter. 0x450[7:0] bid bank id. match the bank id sent by the transmitter. 0x451[3:0] lid0 lane id for lane 0. match the lane id sent by the transmitter on logical lane 0. 0x452[4:0] jesdv jesd204x version. match the version sent by the transmitter (0x0 = jesd204a, 0x1 = jesd204b). 0x459[7:5] 1 f must be programmed in two places. data flow through th e jesd204b receiver the link configuration parameters determine how the serial bits on the jesd204b receiver interface are deframed and passed on to the dacs as data samples. figure 53 shows a detailed flow of the data through the various hardware blocks for mode 4 (l = 4, m = 2, s = 1, f = 1). simplified flow diagrams for all other modes are provided in figure 54 through figure 62. single-link and dual-link configuration the ad9144 uses the settings contained in table 46 and table 47. mode 0 to mode 10 can be used for single-link operation. mode 4 to mode 10 can also be used for dual-link operation. to use dual-link mode, set link_mode (register 0x300[3]) to 1. in dual-link mode, link 1 must be programmed with identical parameters to link 0. to write to link 1, set link_page (register 0x300[2]) to 1. if single-link mode is being used, a small amount of power can be saved by powering down the output buffer for syncout1 , which can be done by setting register 0x203[0] = 1. checking proper configuration as a convenience, the ad9144 provides some quick configuration checks. register 0x030[5] is high if an illegal lmfc_delay is used. register 0x030[3] is high if an unsupported combination of l, m, f, and s is used. register 0x030[2] is high if an illegal k is used. register 0x030[1] is high if an illegal subclassv is used. deskewing and enabling logical lanes after proper configuration, the logical lanes must be deskewed and enabled to capture data. set bit x in register 0x46c to 1 to deskew logical lane x and to 0 if that logical lane is not being used. then, set bit x in register 0x47d to 1 to enable logical lane x and to 0 if that logical lane is not being used.
ad9144 data sheet rev. a | page 50 of 125 data link layer transport layer physical layer deserializer converter 0, sample 0 d15 dac0 dac1 nibble group 0 nibble group 1 deserializer deserializer serial jesd204b data (l = 4) samples split across lanes (hd = 1) 40 bits parallel data (encoded and scrambled) 1 octet per lane (f = 1) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) 2 converters (m = 2) serdinx serdinx j9 j8 j1 j0 j19 j18 j11 j10 lane 0, octet 0 lane 1, octet 0 lane 2, octet 0 lane 3, octet 0 converter 1, sample 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s15 s14 s13 s12 s19 s18 s17 s16 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 s15 s14 s13 s12 s19 s18 s17 s16 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 descrambler 10-bit/8-bit decode serdinx serdinx j9 j8 j1 j0 j19 j18 j11 j10 11675-027 deserializer figure 53. jesd204b mode 4 data deframing
data sheet ad9144 rev. a | page 51 of 125 mode configuration maps table 49 to table 58 contain the spi configuration map for each mode shown in figure 54 through figure 62. figure 54 through figure 62 show the associated data flow through the deframing process of the jesd204b receiver for each of the modes. mode 0 to mode 10 apply to single-link operation. mode 4 to mode 10 also apply to dual-link operation. register 0x300 must be set accordingly for single- or dual-link operation, as previously discussed. additional details regarding all the spi registers can be found in the register maps and descriptions section. table 49. spi configuration mapregister se ttings for jesd204b parameters for mode 0 address setting description 0x453 0x07 or 0x87 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x7: l = 8 lanes per link 0x454 0x00 register 0x454[7:0] = 0x00: f = 1 octet per frame 0x455 0x1f register 0x455[4:0] = 0x1f: k = 32 frames per multiframe 0x456 0x03 register 0x456[7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0xf: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: je sd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x80 register 0x45a[7] = 1: hd = 1; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0xff register 0x46c[7:0] = 0xff: deskew link lane 0 to link lane 7 0x476 0x01 register 0x476[7:0] = 0x01: f = 1 octet per frame 0x47d 0xff register 0x47d[7:0] = 0xff: en able link lane 0 to link lane 7 j15 j14 j9 j8 j7 j6 j1 j0 j7 j6 j1 j0 j15 j14 j9 j8 1 octet per lane (f = 1) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 8) samples split across lanes (hd = 1) nibble group 0 serdinx serdinx serdinx serdinx j15 j14 j9 j8 j7 j6 j1 j0 serdinx serdinx j15 j14 j9 j8 j7 j6 j1 j0 serdinx serdinx converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 nibble group 1 converter 1, sample 0 d15 ... d0 lane 2, octet 0 lane 3, octet 0 nibble group 2 converter 2, sample 0 d15 ... d0 lane 4, octet 0 lane 5, octet 0 nibble group 3 converter 3, sample 0 d15 ... d0 lane 6, octet 0 lane 7, octet 0 4 converters (m = 4) 11675-028 figure 54. jesd204b mode 0 data deframing
ad9144 data sheet rev. a | page 52 of 125 table 50. spi configuration mapregister se ttings for jesd204b parameters for mode 1 address setting description 0x453 0x07 or 0x87 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x7: l = 8 lanes per link 0x454 0x01 register 0x454[7:0] = 0x01: f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x03 register 0x456[7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x21 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x1: s = 2 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0xff register0x46c[7:0] = 0xff: de skew link lane 0 to link lane 7 0x476 0x02 register 0x476[7:0] = 0x02: f = 2 octets per frame 0x47d 0xff register 0x47d[7:0] = 0xff: en able link lane 0 to link lane 7 j15 j14 j1 j0 j15 j14 j1 j0 j15 j14 j1 j0 j15 j14 j1 j0 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 2 samples per converter per frame (s = 2) dac0 dac1 dac2 dac3 serial jesd204b data (l = 8) samples not split across lanes (hd = 0) nibble group 0 nibble group 1 serdinx serdinx serdinx serdinx j15 j14 j1 j0 j15 j14 j1 j0 serdinx serdinx j15 j14 j1 j0 j15 j14 j1 j0 serdinx serdinx conv 0, smpl 0 conv 0, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 0, o 0 l 0, o 1 l 1, o 0 l 1, o 1 4 converters (m = 4) nibble group 2 nibble group 3 conv 1, smpl 0 conv 1, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 2, o 0 l 2, o 1 l 3, o 0 l 3, o 1 nibble group 4 nibble group 5 conv 2, smpl 0 conv 2, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 4, o 0 l 4, o 1 l 5, o 0 l 5, o 1 nibble group 6 nibble group 7 conv 3, smpl 0 conv 3, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 6, o 0 l 6, o 1 l 7, o 0 l 7, o 1 11675-029 figure 55. jesd204b mode 1 data deframing
data sheet ad9144 rev. a | page 53 of 125 table 51. spi configuration mapregister se ttings for jesd204b parameters for mode 2 address setting description 0x453 0x03 or 0x83 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x3: l = 4 lanes per link 0x454 0x01 register 0x454[7:0] = 0x01: f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x03 register 0x456[7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x0f register0x46c[7:0] = 0x0f: de skew link lane 0 to link lane 3 0x476 0x02 register 0x476[7:0] = 0x02: f = 2 octets per frame 0x47d 0x0f register 0x47d[7:0] = 0x0f: enable link lane 0 to link lane 3 j15 j14 j1 j0 j15 j14 j1 j0 serdinx serdinx j15 j14 j1 j0 serdinx j15 j14 j1 j0 serdinx 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 4) samples not split across lanes (hd = 0) converter 0, sample 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 converter 1, sample 0 d15 ... d0 (0) lane 1, octet 0 lane 1, octet 1 converter 2, sample 0 d15 ... d0 (0) lane 2, octet 0 lane 2, octet 1 converter 3, sample 0 d15 ... d0 (0) lane 3, octet 0 lane 3, octet 1 4 converters (m = 4) 11675-030 nibble group 0 nibble group 1 nibble group 2 nibble group 3 figure 56. jesd204b mode 2 data deframing
ad9144 data sheet rev. a | page 54 of 125 table 52. spi configuration mapregister se ttings for jesd204b parameters for mode 3 address setting description 0x453 0x01 or 0x81 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x1: l = 2 lanes per link 0x454 0x03 register 0x454[7:0] = 0x03: f = 4 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x03 register 0x456[7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] =0x0 or 0x1: subclass 0 or subclass 1; register 0x458[4:0] = 0xf: np = 16 bits per sampl e 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x03 register0x46c[7:0] = 0x03: deskew link lane 0 and link lane 1 0x476 0x04 register 0x476[7:0] = 0x04: f = 4 octets per frame 0x47d 0x03 register 0x47d[7:0] = 0x03: en able link lane 0 and link lane 1 j15 j14 j1 j0 j31 j30 j17 j16 4 octets per lane (f = 4) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 2) samples not split across lanes (hd = 0) nibble group 0 serdinx j31 j30 j17 j16 serdinx j15 j14 j1 j0 converter 0, sample 0 nibble group 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 nibble group 1 converter 1, sample 0 d15 ... d0 (0) lane 0, octet 2 lane 0, octet 3 nibble group 2 converter 2, sample 0 d15 ... d0 (0) lane 1, octet 0 lane 1, octet 1 nibble group 3 converter 3, sample 0 d15 ... d0 (0) lane 1, octet 2 lane 1, octet 3 4 converters (m = 4) nibble group 1 nibble group 2 nibble group 3 11675-031 figure 57. jesd204b mode 3 data deframing
data sheet ad9144 rev. a | page 55 of 125 table 53. spi configuration mapregister se ttings for jesd204b parameters for mode 4 address setting description 0x453 0x03 or 0x83 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x3: l = 4 lanes per link 0x454 0x00 register 0x454[7:0] = 0x00: f = 1 octet per frame 0x455 0x1f register 0x455[4:0] = 0x1f: k = 32 frames per multiframe 0x456 0x01 register 0x456[7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x01 register 0x45a[7] = 1: hd = 1; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x0f register0x46c[7:0] = 0x0f: de skew link lane 0 to link lane 3 0x476 0x01 register 0x476[7:0] = 0x01: f = 1 octet per frame 0x47d 0x0f register 0x47d[7:0] = 0x0f: enable link lane 0 to link lane 3 see figure 53 for an illustration of the ad9144 jesd204b mode 4 data deframing process. table 54. spi configuration mapregister se ttings for jesd204b parameters for mode 5 address setting description 0x453 0x03 or 0x83 register 0x453[7] = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x3: l = 4 lanes per link 0x454 0x01 register 0x454[7:0] = 0x01: f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x01 register 0x456[7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x21 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x1: s = 2 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x0f register0x46c[7:0] = 0x0f: de skew link lane 0 to link lane 3 0x476 0x02 register 0x476[7:0] = 0x02: f = 2 octets per frame 0x47d 0x0f register 0x47d[7:0] = 0x0f: enable link lane 0 to link lane 3 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 2 samples per converter per frame (s = 2) dac0 dac1 serial jesd204b data (l = 4) samples not split across lanes (hd = 0) converter 0, sample 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 converter 0, sample 1 d15 ... d0 (1) lane 1, octet 0 lane 1, octet 1 converter 1, sample 0 d15 ... d0 (0) lane 2, octet 0 lane 2, octet 1 converter 1, sample 1 d15 ... d0 (1) lane 3, octet 0 lane 3, octet 1 2 converters (m = 2) 11675-032 j15 j14 j1 j0 j15 j14 j1 j0 serdinx serdinx j15 j14 j1 j0 serdinx j15 j14 j1 j0 serdinx nibble group 0 nibble group 1 nibble group 2 nibble group 3 figure 58. jesd204b mode 5 data deframing
ad9144 data sheet rev. a | page 56 of 125 table 55. spi configuration mapregister se ttings for jesd204b parameters for mode 6 address setting description 0x453 0x01 or 0x81 register 0x453[7] = 0 or 1: scrambling disabled or enabled, register 0x453[4:0] = 0x1: l = 2 lanes per link 0x454 0x01 register 0x454[7:0] = 0x01: f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x01 register 0x456[7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x03 register0x46c[7:0] = 0x03: deskew link lane 0 and link lane 1 0x476 0x02 register 0x476[7:0] = 0x02: f = 2 octets per frame 0x47d 0x03 register 0x47d[7:0] = 0x03: en able link lane 0 and link lane 1 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 serial jesd204b data (l = 2) samples not split across lanes (hd = 0) nibble group 1 converter 1, sample 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lane 1, octet 0 lane 1, octet 1 2 converters (m = 2) j15 j14 j1 j0 j15 j14 j1 j0 serdinx serdinx nibble group 0 converter 0, sample 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lane 0, octet 0 lane 0, octet 1 11675-033 figure 59. jesd204b mode 6 data deframing
data sheet ad9144 rev. a | page 57 of 125 table 56. spi configuration mapregister se ttings for jesd204b parameters for mode 7 address setting description 0x453 0x00 or 0x80 register 0x453[7] = 0 or 1: scrambling disabled or enabled, register 0x453[4:0] = 0x0: l = 1 lane per link 0x454 0x03 register 0x454[7:0] = 0x03: f = 4 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x01 register 0x456[7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x01 register0x46c[7:0] = 0x01: deskew link lane 0 0x476 0x04 register 0x476[7:0] = 0x04: f = 4 octets per frame 0x47d 0x01 register 0x47d[7:0] = 0x01: enable link lane 0 4 octets per lane (f = 4) 16-bit nibble group (n = 16) 1 sample per dac0 dac1 serial jesd204b data (l = 1) samples not split across lanes (hd = 0) nibble group 0 converter 0, sample 0 nibble group 0 d15 ... d0 lane 0, octet 0 lane 0, octet 1 nibble group 2 converter 1, sample 0 d15 ... d0 lane 0, octet 2 lane 0, octet 3 2 converters (m = 2) nibble group 1 j15 j14 j1 j0 j31 j30 j17 j16 serdinx 11675-034 converter per frame (s = 1) figure 60. jesd204b mode 7 data deframing
ad9144 data sheet rev. a | page 58 of 125 table 57. spi configuration mapregister se ttings for jesd204b parameters for mode 9 address setting description 0x453 0x01 or 0x81 register 0x453[7] = 0 or 1: scrambling disabled or enabled, register 0x453[4:0] = 0x1: l = 2 lanes per link 0x454 0x00 register 0x454[7:0] = 0x00: f = 1 octet per frame 0x455 0x1f register 0x455[4:0] = 0x1f: k = 32 frames per multiframe 0x456 0x00 register 0x456[7:0] = 0x00: m = 1 converter per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x01 register 0x45a[7] = 1: hd = 1; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x03 register0x46c[7:0] = 0x03: deskew link lane 0 and link lane 1 0x476 0x01 register 0x476[7:0] = 0x01: f = 1 octet per frame 0x47d 0x03 register 0x47d[7:0] = 0x03: en able link lane 0 and link lane 1 j7 j6 j1 j0 j15 j14 j9 j8 1 octet per lane 16-bit nibble group 1 sample per dac0 serial jesd204b data (l = 2) samples split across lanes (hd = 1) nibble group 0 serdinx serdinx converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 1 converter 11675-035 (f = 1) (n = 16) converter per frame (s = 1) (m = 1) figure 61. jesd204b mode 9 data deframing
data sheet ad9144 rev. a | page 59 of 125 table 58. spi configuration mapregister se ttings for jesd204b parameters for mode 10 address setting description 0x453 0x00 or 0x80 register 0x453[7] = 0 or 1: scrambling disabled or enabled, register 0x453[4:0] = 0x0: l = 1 lane per link 0x454 0x01 register 0x454[7:0] = 0x01: f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455[4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x00 register 0x456[7:0] = 0x00: m = 1 converter per link 0x457 0x0f register 0x457[7:6] = 0x0: always set cs = 0; register 0x457[4:0] = 0x0f: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; regist er 0x458[4:0] = 0xf: np = 16 bits per samp le 0x459 0x20 register 0x459[7:5] = 0x1: set to jesd204b version; register 0x459[4:0] = 0x0: s = 1 (sample/converter)/frame 0x45a 0x00 register 0x45a[7] = 0: hd = 0; register 0x45a[4:0] = 0x00: always set cf = 0 0x46c 0x01 register0x46c[7:0] = 0x01: deskew link lane 0 0x476 0x02 register 0x476[7:0] = 0x02: f = 2 octets per frame 0x47d 0x01 register 0x47d[7:0] = 0x01: enable link lane 0 j15 j14 j1 j0 2 octets per lane 16-bit nibble group 1 sample per dac0 serial jesd204bb data (l = 1) samples split across lanes (hd = 0) nibble group 0 serdinx converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 1 converter (m = 1) 11675-036 (f = 2) (n = 16) converter per frame (s = 1) figure 62. jesd204b mode 10 data deframing
ad9144 data sheet rev. a | page 60 of 125 jesd204b test modes phy prbs testing the jesd204b receiver on the ad9144 includes a prbs pattern checker on the back end of its physical layer. this functionality enables bit error rate (ber) testing of each physical lane of the jesd204b link. the phy prbs pattern checker does not require that the jesd204b link be established. the pattern checker can synchronize with a prbs7, prbs15, or prbs31 data pattern. prbs pattern verification can be done on multiple lanes simultaneously. the error counts for failing lanes are reported for one jesd204b lane at a time. the process for performing prbs testing on the ad9144 is as follows: 1. start sending a prbs7, prbs15, or prbs31 pattern from the jesd204b transmitter. 2. select and write the appropriate prbs pattern to register 0x316[3:2], as shown in table 59. 3. enable the phy test for all lanes being tested by writing to phy_test_en (register 0x315). each bit of register 0x315 enables the prbs test for the corresponding lane. for example, writing a 1 to bit 0 enables the prbs test for physical lane 0. 4. toggle phy_test_reset (register 0x316[0]) from 0 to 1 then back to 0. 5. set phy_prbs_error_threshold (register 0x319 to register 0x317) as desired. 6. write a 0 and then a 1 to phy_test_start (register 0x316[1]). the rising edge of phy_test_start starts the test. 7. wait 500 ms. 8. stop the test by writing phy_test_start (register 0x316[1]) = 0. 9. read the prbs test results. a. each bit of phy_prbs_pass (register 0x31d) corresponds to one serdes lane: 0 is fail, 1 is pass. b. the number of prbs errors seen on each failing lane can be read by writing the lane number to check (0 to 7) in the phy_src_err_cnt (register 0x316[6:4]) and reading the phy_prbs_err_count (register 0x31c to register 0x31a). the maximum error count is 2 24 ? 1 . if all bits of register 0x31c to register 0x31a are high, the maximum error count on the selected lane has been exceeded. table 59. phy prbs pattern selection phy_prbs_pat_sel setting (register 0x316[3:2]) prbs pattern 0b00 (default) prbs7 0b01 prbs15 0b10 prbs31 transport layer testing the jesd204b receiver in the ad9144 supports the short transport layer (stpl) test as described in the jesd204b standard. this test can be used to verify the data mapping between the jesd204b transmitter and receiver. to perform this test, this function must be implemented in the logic device and enabled there. before running the test on the receiver side, the link must be established and running without errors (see the device setup guide section). the stpl test ensures that each sample from each converter is mapped appropriately according to the number of converters (m) and the number of samples per converter (s). as specified in the jesd204b standard, the converter manufacturer specifies what test samples are transmitted. each sample must have a unique value. for example, if m = 2 and s = 2, there are 4 unique samples transmitted repeatedly until the test is stopped. the expected sample must be programmed into the device, and the expected sample is compared to the received sample one sample at a time until all have been tested. the process for performing this test on the ad9144 is as follows: 1. synchronize the jesd204b link. 2. enable the stpl test at the jesd204b tx. 3. select converter 0 sample 0 for testing. write short_tpl_dac_sel (register 0x32c[3:2]) = 0 and short_tpl_sp_sel (register 0x32c[5:4]) = 0. 4. set the expected test sample for converter 0, sample 0. program the expected 16-bit test sample into the short_tpl_ref_sp registers (register 0x32e and register 0x32d). 5. enable the stpl test. write short_tpl_test_en (register 0x32c[0]) = 1. 6. toggle the stpl reset. short_tpl_test_reset (register 0x32c[1]) from 0 to 1 then back to 0. 7. check for failures. read short_tpl_fail (register 0x32f[0]): 0 is pass, 1 is fail. 8. repeat step 3 to step 7 for each sample of each converter, conv 0 sample 0 through conv m ? 1 sample s ? 1 . repeated cgs and ilas test as per section 5.3.3.8.2 of the jesd204b specification, the ad9144 can check that a constant stream of /k28.5/ characters is being received, or that cgs followed by a constant stream of ilas is being received. to run a repeated cgs test, send a constant stream of /k28.5/ characters to the ad9144 serdes inputs. next, set up the device and enable the links as described in the device setup guide section. ensure that the /k28.5/ characters are being received by verifying that the syncoutx has been de- asserted and that cgs has passed for all enabled link lanes by reading register 0x470. program register 0x300[2] = 0 to monitor the status of lanes on link 0, and register 0x300[2] = 1 to monitor the status of lanes on link 1 for dual-link mode.
data sheet ad9144 rev. a | page 61 of 125 to run the cgs followed by a repeated ilas sequence test, follow the device setup guide section; however, before performing the last write (enabling the links), enable the ilas test mode by writing a 1 to register 0x477[7]. then, enable the links. when the device recognizes four cgs characters on each lane, it de-asserts the syncoutx . at this point, the transmitter starts sending a repeated ilas sequence. read register 0x473 to verify that initial lane synchronization has passed for all enabled link lanes. program register 0x300[2] = 0 to monitor the status of lanes on link 0, and register 0x300[2] = 1 to monitor the status of lanes on link 1 for dual-link mode. jesd204b error monitoring disparity, not in table, and unexpected control character errors as per section 7.6 of the jesd204b specification, the ad9144 can detect disparity errors, not in table errors, and unexpected control character errors, and can optionally issue a sync request and reinitialize the link when errors occur. note that the disparity error counter counts all characters with invalid disparity, regardless of whether they are in the 8-bit/10-bit decoding table. this is a minor deviation from the jesd204b specification, which only counts disparity errors when they are in the 8-bit/10-bit decoding table. checking error counts the error count can be checked for disparity errors, not in table errors, and unexpected control character errors. the error counts are on a per lane and per error type basis. note that the lane select and counter select are programmed into register 0x46b, and the error count is read back from the same address. to check the error count, complete the following steps: 1. select the desired link lane and error type of the counter to view. write these to register 0x46b according to table 60. to select a link lane, first se lect a link (register 0x300[2] = 0 to select link 0 or register 0x300[2] = 1 to select link 1 (dual-link only)). note that when using link 1, link lane x refers to logical lane x + 4. 2. read the error count from register 0x46b. note that the maximum error count is equal to the error threshold set in register 0x47c. table 60. error counters addr. bits variable description 0x46b [6:4] lanesel lanesel = x to monitor the error count of link lane x. see the notes on link lane in step 1 of the checking error counts section. [1:0] cntrsel cntrsel = 0b00 for bad running disparity counter. cntrsel = 0b01 for not in table error counter. cntrsel = 0b10 for unexpected control character counter. check for error count over threshold in addition to reading the error count per lane and error type as described in the checking error counts section, the user can check a register to see if the error count for a given error type has reached a programmable threshold. the same error threshold is used for the three error types (disparity, not in table, and unexpected control character). the error counters are on a per error type basis. to use this feature, complete the following steps: 1. program the desired error count threshold into errorthres (register 0x47c). 2. read back the error status for each error type to see if the error count has reached the error threshold. ? disparity errors are reported in register 0x46d. ? not in table errors are reported in register 0x46e. ? unexpected control characters are reported in register 0x46f. error counter and irq control the user can write to register 0x46d and register 0x46f to reset or disable the error counts and to reset the irq for a given lane. note that these are the same registers that are used to report error count over threshold (see the check for error count over threshold section); therefore, the readback is not the value that was written. for each error type 1. select the link lane to access. to select a link lane, first select a link (register 0x300[2] = 0 to select link 0, register 0x300[2] = 1 to select link 1 (dual-link only)). note that when using link 1, link lane x refers to logical lane x + 4. 2. decide whether to reset the irq, disable the error count, and/or reset the error count for the given lane and error type. 3. write the link lane and desired reset or disable action to register 0x46d to register 0x46f according to table 61. table 61. error counter and irq control: disparity (register 0x46d), not in table (register 0x46e), unexpected control character (register 0x46f) bits variable description 7 rstirq rstirq = 1 to reset irq for the lane selected in bits[2:0]. 6 disable_errcnt disable_errcnt = 1 to disable the error count for the lane selected in bits[2:0]. 5 rsterrcntr rsteerrcntr = 1 to reset the error count for the lane selected in bits[2:0]. [2:0] laneaddr laneaddr = x to monitor the error count of link lane x. see the notes on link lane in step 1 of the checking error counts section.
ad9144 data sheet rev. a | page 62 of 125 monitoring errors via syncoutx when one or more disparity, not in table, or unexpected control character error occurs, the error is reported on the syncoutx pins as per section 7.6 of the jesd204b specification. the jesd204b specification states that the syncoutx signal is asserted for exactly 2 frame periods when an error occurs. for the ad9144 , the width of the syncoutx pulse can be programmed to ?, 1, or 2 pclock cycles. the settings to achieve a syncoutx pulse of 2 frame clock cycles are given in table 62. table 62. setting syncoutx error pulse duration 1 these register settings assert the syncoutx signal for 2 frame clock cycles pulse widths. disparity, nit, unexpected control character irqs for disparity, not in table, and unexpected control character errors, error count over the threshold events are available as irq events. enable these events by writing to register 0x47a[7:5]. the irq event status can be read at the same address (register 0x47a[7:5]) after the irqs are enabled. see the error counter and irq control section for information on resetting the irq. see the interrupt request operation section for more information on irqs. errors requiring reinitializing a link reinitialization automatically occurs when four invalid disparity characters are received, as per section 7.1 of the jesd204b specification. when a link reinitialization occurs, the resync request is 5 frames and 9 octets long. the user can optionally reinitialize the link when the error count for disparity errors, not in table errors, or unexpected control characters reaches a programmable error threshold. the process to enable the reinitialization feature for certain error types is as follows: 1. set threshold_mask_en (register 0x477[3]) = 1. note that when this bit is set, unmasked errors do not saturate at either the threshold or maximum value. 2. enable the sync assertion mask for each type of error by writing to sync_assertion_mask (register 0x47b[7:5]) according to table 63. 3. program the desired error counter threshold into errorthres (register 0x47c). 4. for each error type enabled in the sync_assertion_ mask register, if the error counter on any lane reaches the programmed threshold, syncoutx falls, issuing a sync request. note that all error counts are reset when a link reinitialization occurs. the irq does not reset and must be reset manually. table 63. sync assertion mask addr. bit no. bit name description 0x47b 7 baddis_s set to 1 to assert syncoutx if the disparity error count reaches the threshold 6 nit_s set to 1 to assert syncoutx if the not in table error count reaches the threshold 5 ucc_s set to 1 to assert syncoutx if the unexpected control character count reaches the threshold cgs, frame sync, checksum, and ilas monitoring register 0x470 to register 0x473 can be monitored to verify that each stage of jesd204b link establishment has occurred. program register 0x300[2] = 0 to monitor the status of the lanes on link 0, and register 0x300[2] = 1 to monitor the status of the lanes on link 1. bit x of codegrpsyncflag (register 0x470) is high if link lane x received at least four k28.5 characters and passed code group synchronization. bit x of framesyncflag (register 0x471) is high if link lane x completed initial frame synchronization. bit x of goodchksumflg (register 0x472) is high if the checksum sent over the lane matches the sum of the jesd204b parameters sent over the lane during ilas for link lane x. the parameters can be added either by summing the individual fields in registers or summing the packed register. if register 0x300[6] = 0 (default), the calculated checksums are the lower 8 bits of the sum of the following fields: did, bid, lid, scr, l ? 1, f ? 1, k ? 1, m ? 1, n ? 1, subclassv, np ? 1, jesdv, s ? 1, and hd. if register 0x300[6] = 1, the calculated checksums are the lower 8 bits of the sum of register 0x400 to register 0x40c and lid. bit x of initiallanesync (register 0x473) is high if link lane x passed the initial lane alignment sequence. cgs, framesync, checksum, and ilas irqs fail signals for cgs, framesync, checksum, and ilas are available as irq events. enable them by writing to register 0x47a[3:0]. the irq event status can be read at the same address (register 0x47a[3:0]) after the irqs are enabled. write a 1 to register 0x470[7] to reset the cgs irq. write a 1 to register 0x471 to reset the framesync irq. write a 1 to register 0x472 to reset the checksum irq. write a 1 to register 0x473 to reset the ilas irq. see the interrupt request operation section for more information. jesd mode ids pclockfactor (frames/pclock) syncb_err_dur (register 0x312[5:4]) setting 1 0, 4, 9 4 0 (default) 1, 2, 5, 6, 10 2 1 3, 7 1 2
data sheet ad9144 rev. a | page 63 of 125 configuration mismatch irq the ad9144 has a configuration mismatch flag that is available as an irq event. use register 0x47b[3] to enable the mismatch flag (it is enabled by default), and then use register 0x47b[4] to read back its status and reset the irq signal. see the interrupt request operation section for more information. the configuration mismatch event flag is high when the link configuration settings (in regist er 0x450 to register 0x45d) do not match the jesd204b transmitted settings (register 0x400 to register 0x40d). all these registers are paged per link (in register 0x300). note that this function is different from the good checksum flags in register 0x472. the good checksum flags ensure that the transmitted checksum matches a calculated checksum based on the transmitted settings. the configuration mismatch event ensures that the transmitted settings match the configured settings. hardware considerations power supply recommendations the power supply domains are described in table 64. the power supplies can be grouped into separate pcb domains, as show in figure 63. all the ad9144 supply domains must remain as noise free as possible for the best operation. power supply noise has a frequency component that affects performance, and is specified in terms of v rms. figure 64 shows the recommended power supply components. an lc filter on the output of the power supply is recommended to attenuate the noise, and must be placed as close to the ad9144 as possible. an effective filter is shown in figure 63. this filter scheme reduces high frequency noise components. each of the power supply pins of the ad9144 must also have a 0.1 f capacitor connected to the ground plane, as shown in figure 63. place the capacitor as close to the supply pin as possible. adjacent power pins can share a bypass capacitor. connect the ground pins of the ad9144 to the ground plane using vias. power and ground planes solid ground planes are recommended to avoid ground loops and to provide a solid, uninterrupted ground reference for the high speed transmission lines that require controlled impedances. do not use segmented power planes as a reference for controlled impedances unless the entire length of the controlled impedance trace traverses across only a single segmented plane. these and additional guidelines for the topology of high speed transmission lines are described in the jesd204b serial interface inputs (serdin0 to serdin7) section. table 64. power supplies supply domain voltage (v) circuitry dvdd12 1 1.2 digital core pvdd12 2 1.2 dac pll svdd12 3 1.2 jesd204b receiver interface cvdd12 1 1.2 dac clocking iovdd 1.8 spi interface v tt 4 1.2 v tt siovdd33 3.3 sync lvds transmit avdd33 3.3 dac 1 this supply requires a 1.3 v supply when operating at maximum dac sample rates. see table 3 for details. 2 this supply can be combined with cvdd12 on the same regulator with a separate supply filter network and sufficient bypass capacitors near the pins. 3 this supply requires a 1.3 v suppl y when operating at maximum interface rates. see table 4 for details. 4 this supply can be connected to svdd12 and does not need separate circuitry.
ad9144 data sheet rev. a | page 64 of 125 21 25 10f 10h 10f 42 46 v tt 35 67 75 77 85 siovdd33 avdd33 3.3v linear regulator 1.2v linear regulator 1.2v linear regulator 1.2v linear regulator notes 1. unlabeled capacitors are 0.1f, as close as possible to device pin(s), with minimum distance and vias between capacitors and pin(s). 13 14 dvdd12 53 66 iovdd 1.8v fpga vcci o or other system supply pvdd12 cvdd12 svdd12 10h 10h 10f 10f 10f 10f 10f 9 10 56 57 71 76 81 87 1 4 7 8 17 20 22 28 31 32 33 36 39 45 47 50 11675-039 figure 63. jesd204b interface pcb power domain recommendation power input +12v +3.3v ad9144 adm7154-3.3 adm7160-3.3 adp1753 adp2119 adp1741 adp1741 adp2370 svdd12 + v tt dvdd12 cvdd12 + pvdd12 avdd33 iovdd + siovdd33 3.8v 1.8v step-down ddc 1.2mhz, 2a buck 1.2mhz/600khz 800ma 1.2v 1.2v 1.2v 3.3v 3.3v 11675-464 figure 64. power supply connections
data sheet ad9144 rev. a | page 65 of 125 jesd204b serial interface in puts (serdin0 to serdin7) when considering the layout of the jesd204b serial interface transmission lines, there are many factors to consider to maintain optimal link performance. among these factors are insertion loss, return loss, signal skew, and the topology of the differential traces. insertion loss the jesd204b specification limits the amount of insertion loss allowed in the transmission channel (see figure 39). the ad9144 equalization circuitry allows significantly more loss in the channel than is required by the jesd204b specification. it is still important that the designer of the pcb minimize the amount of insertion loss by adhering to the following guidelines: ? keep the differential traces short by placing the ad9144 as near to the transmitting logic device as possible and routing the trace as directly as possible between the devices. ? route the differential pairs on a single plane using a solid ground plane as a reference. ? use a pcb material with a low dielectric constant (<4) to minimize loss, if possible. when choosing between the stripline and microstrip techniques, keep in mind the following considerations: stripline has less loss (see figure 40 and figure 41) and emits less emi, but requires the use of vias that can add complexity to the task of controlling the impedance; whereas microstrip is easier to implement if the component placement and density allow routing on the top layer, and eases the task of controlling the impedance. if using the top layer of the pcb is problematic or the advantages of stripline are desirable, follow these recommendations: ? minimize the number of vias. ? if possible, use blind vias to eliminate via stub effects and use micro vias to minimize via inductance. ? if using standard vias, use the maximum via length to minimize the stub size. for example, on an 8-layer board, use layer 7 for the stripline pair (see figure 65). ? for each via pair, place a pair of ground vias adjacent to them to minimize the impedance discontinuity (see figure 65). layer 1 layer 2 layer 3 layer 4 layer 5 layer 6 layer 7 layer 8 minimize stub effect gnd gnd diff? diff+ y y y add ground vias standard via 11675-040 figure 65. minimizing stub eff ect and adding ground vias for differential stripline traces return loss the jesd204b specification limits the amount of return loss allowed in a converter device and a logic device, but does not specify return loss for the channel. however, every effort must be made to maintain a continuous impedance on the transmission line between the transmitting logic device and the ad9144 . as mentioned in the insertion loss section, minimizing the use of vias, or eliminating them altogether, reduces one of the primary sources for impedance mismatches on a transmission line. maintain a solid reference beneath (for microstrip) or above and below (for stripline) the differential traces to ensure continuity in the impedance of the transmission line. if the stripline technique is used, follow the guidelines listed in the insertion loss section to minimize impedance mismatches and stub effects. another primary source for impedance mismatch is at either end of the transmission line, where care must be taken to match the impedance of the termination to that of the transmission line. the ad9144 handles this internally with a calibrated termination scheme for the receiving end of the line. see the interface power-up and input termination section for details on this circuit and the calibration routine. signal skew there are many sources for signal skew, but the two sources to consider when laying out a pcb are interconnect skew within a single jesd204b link and skew between multiple jesd204b links. in each case, keeping the channel lengths matched to within 15 mm is adequate for operating the jesd204b link at speeds of up to 10.6 gbps. managing the interconnect skew within a single link is fairly straightforward. managing multiple links across multiple devices is more complex. however, follow the 15 mm guideline for length matching. top olo g y structure the differential serdinx pairs to achieve 50 to ground for each half of the pair. stripline vs. microstrip trade- offs are described in the insertion loss section. in either case, it is important to keep these transmission lines separated from potential noise sources such as high speed digital signals and noisy supplies. if using stripline differential traces, route them using a coplanar method, with both traces on the same layer. although this does not offer more noise immunity than the broadside routing method (traces routed on adjacent layers), it is easier to route and manufacture so that the impedance continuity is maintained. an illustration of broadside vs. coplanar differential routing techniques is shown in figure 66. tx diff a tx diff a tx diff b tx active tx diff b tx active broadside differential tx lines coplanar differential tx lines 11675-041 figure 66. broadside vs. coplanar differential stripline routing techniques
ad9144 data sheet rev. a | page 66 of 125 when considering the trace width vs. copper weight and thickness, the speed of the interface must be considered. at multigigabit speeds, the skin effect of the conducting material confines the current flow to the surface. maximize the surface area of the conductor by making the trace width wider to reduce the losses. additionally, loosely couple differential traces to accommodate the wider trace widths. this helps to reduce the crosstalk and minimize the impedance mismatch when the traces must separate to accommodate components, vias, connectors, or other routing obstacles. tightly coupled vs. loosely coupled differential traces are shown in figure 67. tx diff a tx diff a tx diff b tx diff b tightly coupled differential tx lines loosely coupled differential tx lines 11675-042 figure 67. tightly coupled vs. loosely coupled differential traces ac coupling capacitors the ad9144 requires that the jesd204b input signals be ac-coupled to the source. these capacitors must be 100 nf and placed as close as possible to the transmitting logic device. to minimize the impedance mismatch at the pads, select the package size of the capacitor so that the pad size on the pcb matches the trace width as closely as possible. syncoutx , sysref, and clk signals the syncoutx and sysref signals on the ad9144 are low speed lvds differential signals. use controlled impedance traces routed with 100 differential impedance and 50 to ground when routing these signals. as with the serdin0 to serdin7 data pairs, it is important to keep these signals separated from potential noise sources such as high speed digital signals and noisy supplies. separate the syncoutx signal from other noisy signals, because noise on the syncoutx might be interpreted as a request for k characters. the syncoutx signal has two modes of operation available for use. register 0x2a5[0] defaults to 0, which sets the syncoutx swing to normal swing mode. when this bit is set to 1, the syncoutx swing is configured for high swing mode. for more details, see table 8. it is important to keep similar trace lengths for the clk and sysref signals from the clock source to each of the devices on either end of the jesd204b links (see figure 68). if using a clock chip that can tightly control the phase of clk and sysref, the trace length matching requirements are greatly reduced. clock source (ad9516-1, adclk925) lane 0 lane 1 lane n ? 1 lane n device clock device clock sysref sysref sysref trace length sysref trace length device clock trace length device clock trace length tx device rx device 11675-043 figure 68. sysref signal and device clock trace length
data sheet ad9144 rev. a | page 67 of 125 digital datapath input power detection and protection interpolation modes 1, 2, 4, 8 coarse and fine modulation inv sinc digital gain, phase offset, dc offset, and group delay adjustment 11675-049 figure 69. block diagram of digital datapath the block diagram in figure 69 shows the functionality of the digital datapath (all blocks can be bypassed). the digital processing includes an input power detection block; three half- band interpolation filters; a quadrature modulator consisting of a fine resolution nco and f dac /4 and f dac /8 coarse modulation block; an inverse sinc filter; and gain, phase, offset, and group delay adjustment blocks. the interpolation filters take independent i and q data streams. if using the modulation function, i and q must be quadrature data to function properly. note that the pipeline delay changes when digital datapath functions are enabled/disabled. if fixed dac pipeline latency is desired, do not reconfigure these functions after initial configuration. dual paging digital datapath registers are paged to allow configuration of either dac dual independently or both simultaneously. table 65 shows how to use the dual paging register. table 65. paging modes dual_page, reg. 0x008[1:0] duals paged dacs updated 1 a dac0 and dac1 2 b dac2 and dac3 3 (default) a and b dac0, dac1, dac2, and dac3 several functions are paged by dac dual, such as input data format, downstream protection, interpolation, modulation, inverse sinc, digital gain, phase offset, dc offset, group delay, iq swap, datapath prbs, lmfc sync, and nco alignment. data format binary_format (register 0x110[7], paged as described in the dual paging section) controls the expected input data format. by default it is 0, which means that the input data must be in twos complement. it can also be set to 1, which means input data is in offset binary (0x0000 is negative full scale and 0xffff is positive full scale). interpolation filters the transmit path contains three half-band interpolation filters, which each provides a 2 increase in output data rate and a low- pass function. the filters can be cascaded to provide a 4 or 8 interpolation ratio. table 66 shows how to select each available interpolation mode, their usable bandwidths, and their maximum data rates. note that f data = f dac /interpolationfactor. interpolation mode is paged as described in the dual paging section. register 0x030[0] is high if an unsupported interpolation mode is selected. table 66. interpolation modes and usable bandwidth interpolation mode interp_mode, reg 0x112[2:0] usable bandwidth maximum f data (mhz) 1 (bypass) 0x00 0.5 f data 1060 1 2 0x01 0.4 f data 1060 1 4 0x03 0.4 f data 700 8 0x04 0.4 f data 350 1 the maximum speed for 1 and 2 inte rpolation is limited by the jesd204b interface. filter performance the interpolation filters interpolate between existing data in such a way that they minimize changes in the incoming data while suppressing the creation of interpolation images. this is shown for each filter in figure 70. the usable bandwidth (as shown in table 66) is defined as the frequency band over which the filters have a pass-band ripple of less than 0.001 db and an image rejection of greater than 85 db. 0 ?20 ?40 ?60 ?80 ?100 0 0.2 0.4 0.6 0.8 1.0 magnitude (db) frequency ( f dac ) 11675-368 2 4 8 figure 70. all band responses of interpolation filters
ad9144 data sheet rev. a | page 68 of 125 filter performance beyond specified bandwidth the interpolation filters are specified to 0.4 f data (with pass band). the filters can be used slightly beyond this ratio at the expense of increased pass-band ripple and decreased interpolation image rejection. 90 20 0 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 30 40 50 60 70 80 40 41 42 43 44 45 minimum interpolation image rejection (db) maximum pass-band ripple (db) bandwidth (% f data ) 11675-369 pass-band ripple image rejection figure 71. interpolation filter perf ormance beyond specified bandwidth figure 71 shows the performance of the interpolation filters beyond 0.4 f data . note that the ripple increases much slower than the image rejection decreases. this means that if the application can tolerate degraded image rejection from the interpolation filters, more bandwidth can be used. digital modulation the ad9144 has digital modulation features to modulate the baseband quadrature signal to the desired dac output frequency. the coarse modulation modes (f dac /4 and f dac /8) allow modulation by those particular frequencies. the nco fine modulation mode allows modulating by a programmable frequency at the cost of 30 mw to 120 mw, depending on the dac rate. modulation mode is selected as shown in table 67 and paged as described in the dual paging section. table 67. modulation mode selection modulation mode modulation_type, register 0x111[3:2] none 0b00 nco fine modulation 0b01 coarse ? f dac /4 0b10 coarse ? f dac /8 0b11 nco fine modulation this modulation mode uses an nco, a phase shifter, and a complex modulator to modulate the signal by a programmable carrier signal as shown in figure 72. this allows output signals to be placed anywhere in the output spectrum with very fine frequency resolution. the nco produces a quadrature carrier to translate the input signal to a new center frequency. a quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the quadrature carrier is set via an ftw. the quadrature carrier is mixed with the i and q data and then summed into the i and q data paths, as shown in figure 72. ?f dac /2 f carrier < + f dac /2 ftw = ( f carrier / f dac ) 2 48 where ftw is a 48-bit twos complement number. the frequency tuning word is set as shown in table 68 and paged as described in the dual paging section. table 68. nco ftw registers address value description 0x114 ftw[7:0] 8 lsbs of ftw 0x115 ftw[15:8] next 8 bits of ftw 0x116 ftw[23:16] next 8 bits of ftw 0x117 ftw[31:24] next 8 bits of ftw 0x118 ftw[39:32] next 8 bits of ftw 0x119 ftw[47:40] 8 msbs of ftw unlike other registers, the ftw registers are not updated immediately upon writing. instead, the ftw registers update on the rising edge of ftw_update_req (register 0x113[0]). after an update request, ftw_update_ack (register 0x113[1]) must be high to acknowledge that the ftw has updated. sel_sideband (register 0x111[1], paged as described in the dual paging section) is a convenience bit that can be set to use the negative modulation result. this is equivalent to flipping the sign of ftw. 11675-056 interpolation interpolation nco 1 0 ?1 cos( n + ) sin( n + ) i data q data ftw[47:0] sel_sideband out_i out_q + ? nco_phase_offset [15:0] figure 72. nco modulator block diagram
data sheet ad9144 rev. a | page 69 of 125 nco phase offset the phase offset feature allows rotation of the i and q phases. unlike phase adjust, this feature moves the phases of both i and q channels together. phase offset can be used only when using nco fine modulation. ?180 degreesoffset < +180 phaseoffset = ( degreesoffset /180) 2 15 where phaseoffset is a 16-bit twos complement number. the nco phase offset is set as shown in table 69 and paged as described in the dual paging section. because this function is part of the fine modulation block, phase offset is not updated immediately upon writing. instead, it updates on the rising edge of ftw_ update_req (register 0x113[0]) along with the ftw. table 69. nco phase offset registers address value 0x11a phaseoffseti[7:0] 0x11b phaseoffset[15:8] inverse sinc the ad9144 provides a digital inverse sinc filter to compensate the dac roll-off over frequency. the filter is enabled by setting the invsinc_enable bit (register 0x111[7], paged as described in the dual paging section) and is enabled by default. the inverse sinc (sinc ?1 ) filter is a seven-tap fir filter. figure 73 shows the frequency response of sin(x)/x roll-off, the inverse sinc filter, and the composite response. the composite response has less than 0.05 db pass-band ripple up to a frequency of 0.4 f dacclk . to provide the necessary peaking at the upper end of the pass band, the inverse sinc filter shown has an intrinsic insertion loss of approximately 3.8 db; in many cases, this can be partially compensated as described in the digital gain section. 1 0 magnitude (db) ?1 ?2 ?3 ?4 ?5 0 0.05 0.10 0.15 0.20 frequency ( f dac ) 0.25 0.30 0.35 0.45 0.40 0.50 11675-058 sin(x)/x roll-off sinc ?1 filter response composite response figure 73. responses of sin(x)/x roll-off, the sinc ?1 filter, and the composite of the two input signal power detection and protection digital gain, phase adjust, dc offset, and group delay digital gain, phase adjust, and dc offset (as described in the digital gain section, phase adjust section, and dc offset section) allow compensation of imbalances in the i and q paths due to analog mismatches between dac i/q outputs, quadrature modulator i/q baseband inputs, and dac/modulator interface i/q paths. these imbalances can cause the two following issues: ? an unwanted sideband signal to appear at the quadrature modulator output with significant energy. this can be tuned out using digital gain and phase adjust. tuning the quadrature gain and phase adjust values can optimize complex image rejection in single sideband radios or can optimize the error vector magnitude (evm) in zero if (zif) architectures. ? the i/q mismatch can cause lo leakage through a modulator, which can be tuned out using dc offset. group delay allows adjustment of the delay through the dac, which can be used to adjust digital predistortion (dpd) loop delay. digital gain digital gain can be used to independently adjust the digital signal magnitude being fed into each dac. this is useful to balance the gain between i and q channels of a dual or to cancel out the insertion loss of the inverse sinc filter. digital gain must be enabled when using the blanking state machine (see the downstream protection section). if digital gain is disabled, txenx must be tied high. digital gain is enabled by setting the dig_gain_enable bit (register 0x111[5], paged as described in the dual paging section). in addition to enabling the function, the amount of digital gain (gaincode) desired must be programmed. by default, digital gain is enabled and gaincode is 0xaea. 0 gain 4095/2048 ? db dbgain 6.018 db gain = gaincode (1/2048) dbgain = 20 log10( gain ) gaincode = 2048 gain = 2048 10 dbgain /20 where gaincode is a 12-bit unsigned binary number. the i/q digital gain is set as shown in table 70 and paged as described in the dual paging section. the default gaincode (0xaea = 2.7 db), is appropriate to counteract the insertion loss of the inverse sinc filter without causing digital clipping when using 2 interpolation. this value can be read off of figure 73 at 0.25 f dac , as that is the nyquist rate when using a 2 interpolation. recommended gaincode values for 4 and 8 interpolation are 0xbb3 (3.3 db) and 0xbf8 (3.5 db), respectively.
ad9144 data sheet rev. a | page 70 of 125 table 70. digital gain registers address value description 0x111[5] dig_gain_enable set to 1 to enable digital gain 0x13c gaincodei[7:0] i dac lsb gain code 0x13d[3:0] gaincodei[11:8] i dac msb gain code 0x13e gaincodeq[7:0] q dac lsb gain code 0x13f[3:0] gaincodeq[11:8] q dac msb gain code phase adjust ordinarily, the i and q channels of each dac pair have an angle of 90 between them. the phase adjust feature changes the angle between the i and q channels, which can help balance the phase into a modulator. ?14 degreesadjust < 14 phaseadj = ( degreesadjust /14) 2 12 where phaseadj is a 13-bit twos complement number. the phase adjust is set as shown in table 71 and paged as described in the dual paging section. table 71. i/q phase adjustment registers address value description 0x111[4] phase_adj_enable set to 1 to enable phase adjust 0x11c phaseadj[7:0] lsb phase adjust code 0x11d[4:0] phaseadj[12:8] msb phase adjust code dc offset the dc offset feature is used to individually offset the data into the i or q dacs. this feature can be used to cancel lo leakage. the offset is programmed individually for i and q as a 16-bit twos complement number in lsbs, plus a 5-bit twos complement number in sixteenths of an lsb, as shown in table 72. dc offset is paged as described in the dual paging section. ?2 15 lsbsoffset < 2 15 ?16 sixteenthsoffset ? 15 table 72. dc offset registers address value description 0x135[0] dc_offset_on set to 1 to enable dc offset 0x136 lsbsoffseti[7:0] i dac lsb dc offset code 0x137 lsbsoffseti[15:8] i dac msb dc offset code 0x138 lsbsoffsetq[7:0] q dac lsb dc offset code 0x139 lsbsoffsetq[15:8] q dac msb dc offset code 0x13a[4:0] sixteenthsoffseti i dac sub-lsb dc offset code 0x13b[4:0] sixteenthsoffsetq q dac sub-lsb dc offset code group delay group delay can be used to delay both i and q channels together. this can be useful, for example, for dpd loop delay adjust. ?4 dacclockcycles 3.5 groupdelay = ( dacclockcycles 2) + 8 where groupdelay is a 4-bit twos complement number. write groupdelay to group_delay (register 0x014). this feature is paged as described in the dual paging section. i to q swap i_to_q (register 0x111[0], paged as described in the dual paging section) is a convenience bit that can be set to send the i datapath to the q dac. note that this operation occurs at the end of the datapath (after any modulation, digital gain, phase adjust, and phase offset). nco alignment the nco alignment block is used to phase align the nco output from multiple converters. two nco alignment modes are supported by the ad9144 . the first is a sysref alignment mode that phase aligns the nco outputs to the rising edge of a sysref pulse. the second alignment mode is a data key alignment; when this mode is enabled, the ad9144 aligns the nco outputs when a user specified data pattern arrives at the dac input. note that the nco alignment is per dual, and is paged as described in the dual paging section. sysref nco alignment as with the lmfc alignment, in subclass 1, a sysref pulse can be used to phase align the nco outputs of multiple devices in a system and multiple channels on the same device. note that in subclass 0, this alignment mode can be used to align the nco outputs within a device to an internal processing clock edge. no sysref edge is needed in subclass 0, but multichip alignment cannot be achieved. the steps to achieve a sysref nco alignment are as follows: 1. set nco_align_mode (register 0x050[1:0] = 0b01) for sysref nco alignment mode. 2. set nco_align_arm (register 0x050[7] = 1). 3. perform an lmfc alignment to force the nco phase align (see the syncing lmfc signals section). the phase alignment occurs on the next sysref edge. note that if in one-shot sync mode, the lmfc alignment block must be armed by setting register 0x03a[6] = 1. if in continuous mode or one-shot then monitor mode, the lmfc align block does not need to be armed; the nco align automatically trips on the next sysref edge. 4. check the alignment status. if nco phase alignment was successful, nco_align_pass (register 0x050[4]) = 1. if phase alignment failed, nco_align_fail (register 0x050[3]) = 1.
data sheet ad9144 rev. a | page 71 of 125 data key nco alignment in addition to supporting the sysref alignment mode, the ad9144 supports a mode where the nco phase alignment occurs when a user-specified pattern is seen at the dac input. the steps to achieve a data key nco alignment are as follows: 1. set nco_align_mode (register 0x050[1:0]) = 0b10. 2. write the expected 16-bit data key for the i and q datapath into ncokeyi (register 0x051 to register 0x052) and ncokeyq (register 0x053 to register 0x054), respectively. 3. set nco_align_arm (register 0x050[7]) = 1. 4. send the expected 16-bit i and q data keys to the device to achieve nco alignment. 5. check the alignment status. if the expected data key was seen at the dac input, nco_align_mtch (register 0x050[5]) = 1. if nco phase alignment was successful, nco_align_pass (register 0x050[4]) = 1. if phase alignment failed, nco_align_fail (register 0x050[3]) = 1. multiple device nco alignment can be achieved with the data key alignment mode. to achieve multichip nco alignment, program the same expected data key on all devices, arm all devices, and then send the data key to all devices/channels at the same time. nco alignment irq an irq event showing whether the nco align was tripped is available. use register 0x021[4] to enable dac dual a (dac0 and dac1), and then use register 0x025[4] to read back its status and reset the irq signal. use register 0x022[4] to enable dac dual b (dac2 and dac3), and then use register 0x026[4] to read back its status and reset the irq signal. see the interrupt request operation section for more information.
ad9144 data sheet rev. a | page 72 of 125 downstream protection 11675-372 filter and modulation digital gain pdp pdp_protect bsm bsm_protect tx_protect txensm data from lmfc sync logic txenx data to dacs pdp_protect_out 1 0 1 0 protect_out_invert protect_outx 1 0 tx_protect_out 1 0 spi_protect_out spi_protect protect outx generation figure 74. downstream pr otection block diagram the ad9144 has several blocks designed to protect the power amplifier (pa) of the system, as well as other downstream blocks. it consists of a power detection and protection (pdp) block, a blanking state machine (bsm), and a transmit enable state machine (txensm). the pdp block can be used to monitor incoming data. if a moving average of the data power goes above a threshold, the pdp block provides a signal (pdp_protect) that can be routed externally. the txensm is a simple block that controls delay between txenx and the tx_protect signal. the tx_protect signal is used as an input to the bsm, and its inverse can optionally be routed externally. optionally, the txensm can also power down its associated dac dual. the bsm gently ramps data entering the dac and flushes the datapath. the bsm is activated by the tx_protect signal or automatically by the lmfc sync logic during a rotation. for proper function, digital gain must be enabled; tie txen high if disabling digital gain. finally, some simple logic takes the outputs from each of those blocks and uses them to generate a desired protect_outx signal on an external pin. this signal can be used to enable/disable downstream components, such as a pa. power detection and protection the input signal pdp block is designed to detect the average power of the dac input signal and to prevent overrange signals from being passed to the next stage, which may potentially cause destructive breakdown on power sensitive devices, such as pas. the protection function provides a signal (pdp_protect) that can be routed externally to shut down a pa. the pdp block uses a separate path with a shorter latency than the datapath to ensure that pdp_protect is triggered before the overrange signal reaches the analog dac cores. the sum of the i 2 and q 2 are calculated as a representation of the input signal power (only the top six msbs of data samples are used). the calculated sample power numbers are accumulated through a moving average filter whose output is the average of the input signal power in a certain number of samples. when the output of the averaging filter exceeds the threshold, the internal signal pdp_protect goes high, which can optionally be configured to trigger a signal on the protect_outx. the pdp block is configured as shown in table 73 and paged as described in the dual paging section. the choice of pdp_avg_time (register 0x062) and pdp_threshold (register 0x060 to register 0x061) for effective protection are application dependent. experiment with real-world vectors to ensure proper configuration. the pdp_ power readback (register 0x063 to register 0x064) can help by storing the maximum power when a set threshold was passed.
data sheet ad9144 rev. a | page 73 of 125 table 73. pdp registers addr. bit no. value description 0x060 [7:0] pdp_threshold[7:0] power that triggers pdp_protect. 8 lsbs. 0x061 [4:0] pdp_threshold[12:8] 5 msbs. 0x062 7 pdp_enable set to 1 to enable pdp. [3:0] pdp_avg_time can be set from 0 to 10. averages across 2 (9 + pdp_avg_time) , iq sample pairs. 0x063 [7:0] pdp_power[7:0] if pdp_threshold is crossed, this reads back the maximum power seen. if not, this reads back the instantaneous power. 8 lsbs. 0x064 [4:0] pdp_power[12:8] 5 msbs. power detection and protection irq the pdp_protect signal is available as an irq event. use register 0x021[7] to enable pdp_protect for dual a (dac0 and dac1), and then use register 0x025[7] to read back its status and reset the irq signal. use register 0x022[7] to enable pdp_protect for dual b (dac2 and dac3), and then use register 0x026[7] to read back its status and reset the irq signal. see the interrupt request operation section for more information. transmit enable state machine the txensm is a simple block that controls the delay between the txenx signal and the tx_protect signal. this signal is used as an input to the bsm and its inverse can be routed to an external pin (protect_outx) to turn downstream components on or off as desired. the txenx signal can be used to power down their associated dac duals. if duala_mask (register 0x012[0]) = 1, a falling edge of txenx causes dac dual a (dac0 and dac1) to power down. if dualb_mask (register 0x012[1]) = 1, a falling edge of txenx causes dac dual b (dac2 and dac3) to power down. on a rising edge of txenx, without duala_mask and dualb_mask enabled, the output is valid after the bsm settles (see the blanking state machine (bsm) section). if the masks are enabled, an additional delay is imposed; the output is not valid until the bsm settles and the dacs fully power on (nominally an additional ~35 s). the txensm is configured as shown in table 74 and is paged as described in the dual paging section. table 74. txensm registers addr. bit no. value description 0x11f [7:6] fall_counters number of fall counters to use (1 to 2). [5:4] rise_counters number of rise counters to use (0 to 2). 0x121 [7:0] rise_count_0 delay tx_protect rise from txen rising edge by 32 rise_count_0 dac clock cycles. 0x122 [7:0] rise_count_1 delay tx_protect rise from txen rising edge by 32 rise_count_1 dac clock cycles. 0x123 [7:0] fall_count_0 delay tx_protect rise from txen rising edge by 32 fall_count_0 dac clock cycles. must be at least 0x12. 0x124 [7:0] fall_count_1 delay tx_protect rise from txen rising edge by 32 fall_count_1 dac clock cycles. blanking state machine (bsm) the bsm gently ramps data entering the dac and flushes the datapath. on a falling edge of tx_protect (the txenx signal delayed by the txensm), the datapath holds the latest data value and the digital gain gently ramps from its set value to 0. at the same time, the datapath is flushed with zeroes. on a rising edge of tx_protect , the txenx signal is delayed by the txensm; data is allowed to flow through the datapath again, and the digital gain gently ramps the data from 0 up to the set digital gain. both of these functions are also triggered automatically by the lmfc sync logic during a rotation to prevent glitching on the output. ramping for proper ramping, digital gain must be enabled; tie txen high if disabling digital gain. the step size to use when ramping gain to 0 or its assigned value can be controlled via the gain_ramp_down_step registers (register 0x142 and register 0x143) and the gain_ramp_ up_step registers (register 0x140 and register 0x141). these registers are paged as described in the dual paging section. the current bsm state can be read back as shown in table 75.
ad9144 data sheet rev. a | page 74 of 125 table 75. blanking state machine ramping readbacks address value description 0x147[7:6] 0b00 data is being held at midscale. 0b01 ramping gain to 0. data ramping to midscale. 0b10 ramping gain to assigned value. data ramping to normal amplitude. 0b11 data at normal amplitude. blanking state machine irq blanking completion is available as an irq event. use register 0x021[5] to enable blanking completion for dac dual a (dac0 and dac1), and then use register 0x025[5] to read back its status and reset the irq signal. use register 0x022[5] to enable blanking completion for dac dual b (dac2 and dac3), and then use register 0x026[5] to read back its status and reset the irq signal. see the interrupt request operation section for more information. protect_outx generation register 0x013 controls which signals are ored into the external protect_outx signal. register 0x11f[2] can be used to invert the protect_outx signal, by default, protect_outx is high when the output is valid. both of these registers are paged as described in the dual paging section. table 76. protect_outx registers addr. bit no. value description 0x013 6 pdp_protect_out 1: pdp block triggers protect_out 5 tx_protect_out 1: txensm triggers protect_out 3 spi_protect_out 1: spi_protect triggers protect_out 2 spi_protect sets spi_protect 0x11f 2 protect_out_ invert inverts protect_outx datapath prbs the datapath prbs can be used to verify that the ad9144 datapath is receiving and correctly decoding data. the datapath prbs verifies that the jesd204b parameters of the transmitter and receiver match, that the lanes of the receiver are mapped appropriately, that the lanes have been appropriately inverted, if necessary, and in general that the start-up routine has been implemented correctly. the datapath prbs is paged as described in the dual paging section. to run the datapath prbs test, complete the following steps: 1. set up the device in the desired operating mode. see the device setup guide section for details on setting up the device. 2. send prbs7 or prbs15 data. 3. write register 0x14b[2] = 0 for prbs7 or 1 for prbs15. 4. write register 0x14b[1:0] = 0b11 to enable and reset the prbs test. 5. write register 0x14b[1:0] = 0b01 to enable the prbs test and release reset. 6. wait 500 ms. 7. check the status by checking the irq for dac0 to dac3 prbs as described in the datapath prbs irq section. 8. if there are failures, set register 0x008 = 0x01 to view the status of dual a (dac0/dac1). set register 0x08 = 0x02 to view the status of dual b (dac2/dac3). 9. read register 0x14b[7:6]. bit 6 is 0 if the i dac of the selected dual has any errors. bit 7 is 0 if the q dac of the selected dual has any errors. this must match the irq. 10. read register 0x14c to read the error count for the i dac of the selected dual. read register 0x14d to read the error count for the q dac of the selected dual. note that the prbs processes 32 bits at a time, and compares the 32 new bits to the previous set of 32 bits. it detects (and reports) only 1 error in every group of 32 bits; therefore, the error count partly depends on when the errors are seen. for example ? bits: 32 good, 31 good, 1 bad; 32 good [2 errors] ? bits: 32 good, 22 good, 10 bad; 32 good [2 errors] ? bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good [3 errors] datapath prbs irq the prbs fail signals for each dac are available as irq events. use register 0x020[3:0] to enable the fail signals, and then use register 0x024[3:0] to read back their statuses and reset the irq signals. see the interrupt request operation section for more information. dc test mode as a convenience, the ad9144 provides a dc test mode, which is enabled by setting register 0x520[1] to 1 and clearing register 0x146[0] to 0. when this mode is enabled, the datapath is given 0 (midscale) for its data. register 0x146[0] must be set to 1 for all other modes of operation. in conjunction with dc offset, this test mode can provide desired dc data to the dacs. this test mode can also provide sinusoidal data to the dacs by combining digital modulation (to set frequency) and dc offset (to set amplitude). see the dc offset section.
data sheet ad9144 rev. a | page 75 of 125 interrupt request operation the ad9144 provides an interrupt request output signal on pin 60 ( irq ) that can be used to notify an external host processor of significant device events. on assertion of the interrupt, query the device to determine the precise event that occurred. the irq pin is an open-drain, active low output. pull the irq pin high external to the device. this pin can be tied to the interrupt pins of other devices with open-drain outputs to wire; or these pins together. figure 75 shows a simplified block diagram of how the irq blocks works. if irq_en is low, the interrupt_source signal is set to 0. if irq_en is high, any rising edge of event causes the interrupt_source signal to be set high. if any interrupt_source signal is high, the irq pin is pulled low. interrupt_source can be reset to 0 by either an irq_reset signal or a device_reset. depending on status_mode, the event_status bit reads back event or interrupt_source. the ad9144 has several irq register blocks, which can monitor up to 75 events (depending on device configuration). certain details vary by irq register block as described in table 77. table 78 shows which registers the irq_en, irq_reset, and status_mode signals in figure 75 are coming from, as well as the address where event_status is read back. table 77. irq register block details register block event reported event_status 0x01f to 0x026 per chip interrupt_source if irq is enabled; if not, it is event 0x46d to 0x46f; 0x470 to 0x473; 0x47a per link and lane interrupt_source if irq is enabled; if not, 0 0x47b[4] per link interrupt_source if irq is enabled; if not, 0 interrupt service routine interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. enable the events that require host action so that the host is notified when they occur. for events requiring host intervention upon irq activation, run the following routine to clear an interrupt request: 1. read the status of the event flag bits that are being monitored. 2. disable the interrupt by writing 0 to irq_en. 3. read the event source. for register 0x01f to register 0x026, event_status has a live readback. for other events, see their registers. 4. perform any actions required to clear the cause of the event. in many cases, no specific actions are required. 5. verify that the event source is functioning as expected. 6. clear the interrupt by writing 1 to irq_reset. 7. enable the interrupt by writing 1 to irq_en. irq_en event device_reset event_status interrupt_source irq_en status_mode 1 0 1 0 other interrupt sources irq irq_reset 11675-060 figure 75. simplified schematic of irq circuitry table 78. irq register block a ddress of irq signal details register block address of irq signals irq_en irq_reset status_mode event_status 0x01f to 0x026 0x01f to 0x022; r/w per ch ip 0x023 to 0x026; w per chip status_mode = irq_en 0x023 to 0x26; r per chip 0x46d to 0x46f 0x47a; w per link 0x46d to 0x46f; w per link and lane not applicable, status_mode = 1 0x47a; r per link 0x470 to 0x473 0x47a; w per link 0x470 to 0x473; w per link not applicable, status_mode = 1 0x47a; r per link 0x47b[4] 0x47b[3]; r/w per link; 1 by default 0x47b[4]; w per link not applicable, status_mode = 1 0x47b[4]; r per link
ad9144 data sheet rev. a | page 76 of 125 dac input clock configurations the ad9144 dac sample clock (dacclk) can be sourced directly through clk (pin 2 and pin 3) or by clock multiplication through the clk differential input. clock multiplication employs the on-chip pll that accepts a reference clock operating at a submultiple of the desired dacclk rate. the pll then multiplies the reference clock up to the desired dacclk frequency, which is used to generate all the internal clocks required by the dac. the clock multiplier provides a high quality clock that meets the performance requirements of most applications. using the on-chip clock multiplier removes the burden of generating and distributing the high speed dacclk. the second mode bypasses the clock multiplier circuitry and allows dacclk to be sourced directly to the dac core. this mode enables the user to source a very high quality clock directly to the dac core. driving the clk inputs the clk differential input circuitry is shown in figure 76 as a simplified circuit diagram of the input. the on-chip clock receiver has a differential input impedance of 10 k. it is self biased to a common-mode voltage of approximately 600 mv. the inputs can be driven by differential pecl or lvds drivers with ac coupling between the clock source and the receiver. clk+ clk? 600mv 5k? 5k? 11675-061 figure 76. clock receiver input simplified equivalent circuit the minimum input drive level to the differential clock input is 400 mv p-p differential. the optimal performance is achieved when the clock input signal is between 800 mv p-p differential and 1000 mv p-p differential. whether using the on-chip clock multiplier or sourcing the dacclk directly (the clk pins are used in both cases), it is necessary that the input clock signal to the device has low jitter and fast edge rates to optimize the dac noise performance. direct clocking with a low noise clock produces the lowest noise spectral density at the dac outputs. the clocks and clock receiver are powered down by default. the clocks must be enabled by writing to register 0x080. to enable all clocks on the device, write register 0x080 = 0x00. register 0x080, bit 7 powers up the clocks for dac0 and dac1. bit 6 powers up the clocks for dac2 and dac3, bit 5 powers up the digital clocks, bit 4 powers up the serdes clocks, and bit 3 powers up the clock receiver. dac pll fixed register writes to optimize the pll across all operating conditions, the register writes in table 79 are recommended. these writes properly set up the dac pll, including the loop filter and the charge pump. table 79. dac pll fixed register writes register address register value description 0x087 0x62 optimal dac pll loop filter settings 0x088 0xc9 optimal dac pll loop filter settings 0x089 0x0e optimal dac pll loop filter settings 0x08a 0x12 optimal dac pll charge pump settings 0x08d 0x7b optimal dac ldo settings for dac pll 0x1b0 0x00 power dac pll blocks when power machine disabled 0x1b9 0x24 optimal dac pll charge pump settings 0x1bc 0x0d optimal dac pll vco control settings 0x1be 0x02 optimal dac pll vco power control settings 0x1bf 0x8e optimal dac pll vco calibration settings 0x1c0 0x2a optimal dac pll lock counter length setting 0x1c1 0x2a optimal dac pll charge pump setting 0x1c4 0x7e optimal dac pll varactor settings clock multiplication the on-chip pll clock multiplier circuit can be used to generate the dac sample rate clock from a lower frequency reference clock. the pll is integrated on-chip, including the vco and the loop filter. the vco operates over the frequency range of 6 ghz to 12 ghz. the pll configuration parameters must be programmed before the pll is enabled. step by step instructions on how to program the pll can be found in the starting the pll section. the functional block diagram of the clock multip lier is shown in figure 79. the clock multiplication circuit generates the dac sampling clock from the refclk input, which is fed in on the clk differential pins (pin 2 and pin 3). the frequency of the refclk input is referred to as f ref . the refclk input is divided by the variable refdivfactor. select the refdivfactor variable to ensure that the frequency into the phase frequency detector (pfd) block is between 35 mhz and 80 mhz. the valid values for refdivfactor are 1, 2, 4, 8, 16, or 32. each refdivfactor maps to the appropriate ref_div_mode register control according to table 80. the ref_div_mode register is programmed through register 0x08c[2:0].
data sheet ad9144 rev. a | page 77 of 125 table 80. mapping of refdivfactor to ref_div_mode dac reference frequency range (mhz) divide by (refdivfactor) ref_div_mode, reg. 0x08c[2:0] 35 to 80 1 0 80 to 160 2 1 160 to 320 4 2 320 to 640 8 3 640 to 1000 16 4 the range of f ref is 35 mhz to 1 ghz, and the output frequency of the pll is 420 mhz to 2.8 ghz. use the following equations to determine the refdivfactor: mhz80 mhz35 ? ? or refdivfact f ref (1) where: refdivfactor is the reference divider division ratio. f ref is the reference frequency on the clk input pins. the bcount value is the divide ratio of the loop divider. it is set to divide the f dacclk to frequency match the f ref /refdivfactor. select bcount so that the following equation is true: or refdivfact f bcount f ref dacclk ? ? 2 (2) where: bcount is the feedback loop divider ratio. f dacclk is the dac sample clock. the bcount value is programmed with bits[7:0] of register 0x085. it is programmable from 6 to 127. the pfd compares f ref /refdivrate to f dac /(2 bcount) and pulses the charge pump up or down to control the frequency of the vco. a low noise vco is tunable over an octave with an oscillation range of 6 ghz to 12 ghz. the clock multiplication circuit operates such that the vco outputs a frequency, f vco . r lodivfacto ff dacclk vco ?? (3) and from equation 2, the dac sample clock frequency, f dacclk , is equal to or refdivfact f bcount f ref dacclk ??? 2 (4) the lodivfactor is chosen to keep f vco in the operating range between 6 ghz and 12 ghz. the valid values for lodivfactor are 4, 8, and 16. each lodivfactor maps to a lo_div_mode value. the lo_div_mode (register 0x08b[1:0]) value is programmed as described in table 81. table 81. dac vco divider selection dac frequency range (mhz) divide by (lodivfactor) lo_div_mode, register 0x08b[1:0] >1500 4 1 750 to 1500 8 2 420 to 750 16 3 table 82 lists some common frequency examples for the refdivfactor, lodivfactor, and bcount values that are needed to configure the pll properly. table 82. common frequency examples frequency (mhz) f dacclk (mhz) f vco (mhz) refdiv- factor lodiv- factor bcount 368.64 1474.56 11796.48 8 8 16 184.32 1474.56 11796.48 4 8 16 307.2 1228.88 9831.04 8 8 16 122.88 983.04 7864.35 2 8 8 61.44 983.04 7864.35 1 8 8 491.52 1966.08 7864.35 8 4 16 245.76 1966.08 7864.35 4 4 16 loop filter the rf pll filter is fully integrated on-chip and is a standard passive third-order filter with five 4-bit programmable components (see figure 77). the c1, c2, c3, r1, and r3 filter components are programmed with register 0x087 through register 0x089, as described in the dac pll fixed register wr ites sect ion. r1 from charge pump to vco to vco ldo c1 c2 c3 r3 11675-062 figure 77. loop filter charge pump the charge pump current is 6-bit programmable and varies from 0.1 ma to 6.4 ma in 0.1 ma steps. the charge pump current is programmed into register 0x08a for the dac pll, as shown in the dac pll fixed register writes section. the charge pump calibration must be run one time during chip initialization to reduce reference spurs. this calibration is on by default. up down c harge pump current = 0.1ma to 6.4ma to loop filter 11675-063 figure 78. charge pump
ad9144 data sheet rev. a | page 78 of 125 charge pump calibration is run during the first power-up of the pll, and the coefficient of the calibration is held for all subsequent starts. the pll is enabled by writing 0x10 into register 0x083; however, the configuration registers must be programmed before the pll is enabled. the calibration tries to match the up and down current, which minimizes the spurs at the reference frequency that appears at the dac output. the charge pump calibration takes 64 reference clock cycles. bit 5 in register 0x084 notifies the user that the charge pump calibration is completed and is valid. temperature tracking when properly configured, the device automatically selects one of the 512 vco bands. the pll settings selected by the device ensure that the pll remains locked over the full ?40c to +85c operating temperature range of the device without further adjustment. the pll remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes. check the pll lock bit to make sure that the calibration completed properly. the pll lock bit is bit 1 of register 0x084. to properly configure temperature tracking, follow the settings in the dac pll fixed register writes section and the f vco dependent spi writes shown in table 83. table 83. vco control lookup table reference vco frequency range (ghz) register 0x1b5 setting register 0x1bb setting register 0x1c5 setting f vco < 6.3 0x08 0x03 0x07 6.3 f vco < 7.25 0x09 0x03 0x06 f vco 7.25 0x09 0x13 0x06 starting the pll the programming sequence for the dac pll is as follows: 1. program the registers in the dac pll fixed register wr ites sect ion. 2. determine the vco frequency based on the dac frequency requirements. 3. determine the vco divider ratio to achieve the desired dac frequency. program the vco divider ratio in register 0x08b[1:0]. 4. determine the bcount ratio to achieve the desired pll reference frequency (35 mhz to 80 mhz). program the bcount ratio in register 0x085[7:0]. 5. determine the reference divider ratio to achieve the desired pll reference frequency. program the reference divider ratio in register 0x08c[2:0]. 6. based on the f vco found in step 2, write the temperature tracking registers as shown in table 83. 7. enable the dac pll synthesizer by setting register 0x083[4] to 1. register 0x084[5] notifies the user that the dac pll calibration is completed and is valid. register 0x084[1] notifies the user that the pll has locked. register 0x084[7] and register 0x084[6] notify the user that the dac pll hit the upper or lower edge of its operating band, respectively. if either of these bits are high, recalibrate the dac pll by setting register 0x083[7] to 0 and then 1. dac pll irq the dac pll lock and lost signals are available as irq events. use register 0x01f[5:4] to enable these signals, and then use register 0x023[5:4] to read back their statuses and reset the irq signals. see the interrupt request operation section for more information. 11675-064 lc vco 6ghz to 12ghz 4-bit programmable, integrated loop filter charge pump pfd 80mhz max retimer up down f ref 35mhz to 1ghz b counter refdivfactor 0.1ma to 6.4ma fo cal alc cal cal control bits r1 r3 c1 c2 c3 vco ldo mux/selectable buffers 2 2 iq iq iq 2 2 >1.5ghz 750mhz to 1.5ghz <750mhz dac clock 420mhz to 2.8ghz bcount (integer feedback divider) range = 6 to 127 lodivfactor = 4, 8, 16 2 2 4 8 16 1 figure 79. device clock pll block diagram
data sheet ad9144 rev. a | page 79 of 125 analog outputs transmit dac operation figure 80 shows a simplified block diagram of the transmit path dacs. the dac core consists of a current source array, a switch core, digital control logic, and full-scale output current control. the dac full-scale output current (i outfs ) is nominally 20.48 ma. the output currents from the outx pins are complementary, meaning that the sum of the two currents always equals the full- scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. out3+ out3? out2+ out2? out1+ out1? out0+ out0? current scaling q dacs full-scale adjust i dacs full-scale adjust 1.2v 4k? i120 dac3 dac2 dac1 dac0 11675-065 figure 80. simplified block diagram of dac core the dac has a 1.2 v band gap reference. a 4 k external resistor, r set , must be connected from the i120 pin to the ground plane. this resistor, along with the reference control amplifier, sets up the correct internal bias currents for the dac. because the full-scale current is inversely proportional to this resistor, the tolerance of r set is reflected in the full-scale output amplitude. dacfsc_x (where x is a number from 0 to 3 that corresponds to dac0 through dac3) is a 10-bit twos complement value that controls the full-scale current of each of the four dac outputs. these values are stored in register 0x040 to register 0x047, as shown in table 84. the typical full-scale current for each dac is given by: i outfs = 20.45 + ( dacfsc_x 6.55 ma)/2 (10 ? 1) for nominal values of v ref (1.2 v), r set (4 k), and dacfsc_x (0, which is midscale in twos complement), the full-scale current of the dac is typically 20.48 ma. the dac full-scale current can be adjusted from 13.9 ma to 27.0 ma, by programming the appropriate dacfsc_x values in register 0x040 to register 0x047. analog output full-scale current vs. dac gain code is plotted in figure 81. table 84. dac full-scale current registers address value description 0x040[1:0] dacfsc_0[9:8] dual a i dac msb gain code 0x041[7:0] dacfsc_0[7:0] dual a i dac lsb gain code 0x042[1:0] dacfsc_1[9:8] dual a q dac msb gain code 0x043[7:0] dacfsc_1[7:0] dual a q dac lsb gain code 0x044[1:0] dacfsc_2[9:8] dual b i dac msb gain code 0x045[7:0] dacfsc_2[7:0] dual b i dac lsb gain code 0x046[1:0] dacfsc_3[9:8] dual b q dac msb gain code 0x047[7:0] dacfsc_3[7:0] dual b q dac lsb gain code 28 ?512 512 384 256 128 0 gain dac code i outfs (ma) ?128 ?256 ?384 26 24 22 20 18 16 14 12 11675-066 figure 81. dac full-scale current (i outfs ) vs. dac gain code transmit dac transfer function the output currents from the outx+ and outx? pins are complementary, meaning that the sum of the positive and negative currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. outx provides the maximum output current when all bits are high for binary data. the output currents vs. daccode for the dac outputs using binary format are expressed as outfs n bin outp i daccode i u 12 (5) outp outfs outn iii (6) where daccode bin is the 16-bit input to the dac in unsigned binary. daccode bin has a range of 0 to 2 n ? 1. if the data format is twos complement, the output currents are expressed as outfs n n twos outp i daccode i u 12 2 1 (7) outp outfs outn iii (8) where daccode twos is the 16-bit input to the dac in twos complement. daccode twos has a range of ?2 n ? 1 to 2 n ? 1 ? 1.
ad9144 data sheet rev. a | page 80 of 125 powering down unused dacs power down any unused dac outputs to avoid burning excess power. the dac power downs are located in register 0x011. register 0x011, bit 6 corresponds to dac0, bit 5 corresponds to dac1, bit 4 corresponds to dac2, and bit 3 corresponds to dac3. write a 1 to each bit to power down the appropriate dacs. register 0x011, bit 7 and bit 2, must stay low to enable the band gap and dac master bias, respectively. for more information on which dacs to power down, see the dac power-down setup section. self calibration the ad9144 has a self calibration feature that improves the dac dc and ac linearity in zero or low if applications. the performance improvement includes the inl/dnl, second and fourth harmonic distortions (hd2 and hd4), and second-order intermodulation distortion (imd2) of the device. figure 82 and figure 83 show the typical dac inl and dnl before and after the calibration. figure 84 and figure 85 show the calibration effect on the hd2, hd4, and imd2 performance. the improvement from calibration decreases with the dac output frequency. for improvement in hd2 and hd4, it is recommended to run the calibration routine when the desired output frequency is below 100 mhz. for improvement in imd2, it is recommended to run the routine when the desired output frequency is below 200 mhz. a single run of the routine is sufficient to obtain the desired performance for both ac and dc performance. 4 ?4 ?3 ?2 ?1 0 1 2 3 070k 11675-088 60k 50k 40k 30k 20k 10k inl (lsb) dac gain code calibration off calibration on figure 82. pre-calibration and post-calibration, inl 4 ?2 ?1 0 1 2 3 070k 11675-089 60k 50k 40k 30k 20k 10k dnl (lsb) dac gain code calibration off calibration on figure 83. pre-calibration and post-calibration, dnl ? 40 ?100 ?90 ?80 ?70 ?60 ?50 0 300 250 200 150 100 50 sfdr (dbc) f out (mhz) calibration off calibration on second harmonic fourth harmonic 11675-095 figure 84. pre-calibration and post-calibration, hd2 and hd4 ? 60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 300 250 200 150 100 50 imd2 (dbc) f out (mhz) calibration off calibration on 11675-096 figure 85. pre-calibration and post-calibration, imd2
data sheet ad9144 rev. a | page 81 of 125 when using all four dacs, follow the procedure in table 85 to perform a device self calibration. however, when using fewer than four dacs, follow the calibration routine shown in table 86. table 85. device self calibration procedure for 4-converter setup addr. spi data byte description 0x0e7 0x38 enable calibration clock. 0x0e8 0x0f calibrate all dacs. 0x0ed 0xa2 configure initial value. 0x0e2 0x01 enable averaged calibration. 0x0e2 0x03 start averaged calibration. read 0x023[7:6] 0b10 cal_pass (register 0x023[7]) = 1 to indicate that the calibration passed. if cal_pass = 0, check cal_fail (register 0x023[6]). if both cal_pass = 0 and cal_fail = 0, calibration is either still running or it never ran. try waiting ~100 ms and reread cal_pass and cal_fail, or rerun the calibration routine. 0x0e7 0x30 disable calibration clock. if using fewer than four converters, use the calibration routine in table 86. see dac power-down setup for notes on which dacs to power down when using fewer than four converters. table 86. device self calibration procedure with fewer than four converters enabled addr. bit spi data byte description 0x0e7 0x38 use highest comparator speed and set calibration clock divider 0x0e8 select dacs to calibrate 3 0b0 or 0b1 1 if dac3 is enabled 2 0b0 or 0b1 1 if dac2 is enabled 1 0b0 or 0b1 1 if dac1 is enabled 0 0b0 or 0b1 1 if dac0 is enabled 0x0ed 0xa2 configure initial value 0x0e9 0x01 enable calibration 0x0e9 0x03 start calibration 0x0e7 0x30 disable calibration clock for each dac calibrated, check the calibration status by writing a 1 in the corresponding bit of cal_page (register 0x0e8) and reading register 0x0e9. if the calibration completed correctly, cal_fin (register 0x0e9[7]) = 1 to indicate that calibration is complete, and register 0x0e9[6:4] = 0 to indicate that no errors occurred. the post-calibration result is a function of operating temperature. a set of calibration coefficients obtained at one temperature may not be the optimal setting for a different temperature. figure 86 and figure 87 show the typical temperature drift effect after a single run calibration. for optimal performance, run the calibration again when the operating temperature changes significantly. note that it is recommended to power down the dac outputs when running the calibration routine. if continuous transmission is required in the system, running the calibration again during the operation may not be an option. in this case, it is recommended to perform a calibration at the average temperature of the operating temperature range and to use the same set of coefficients during the operation. this results in the best overall performance over temperature. sfdr (dbc) ? 40 ?50 ?60 ?70 ?80 ?90 ?100 0 50 100 150 f out (mhz) 200 250 300 ?40c +25c +85c second harmonic fourth harmonic 11675-486 figure 86. post-calibration hd2 and hd4 over temperature, calibrated at 25c imd2 (dbc) ? 60 ?65 ?70 ?75 ?80 ?90 ?85 ?95 ?100 050100150 f out (mhz) 200 250 300 ?40c +25c +85c 11675-487 figure 87. post-calibration imd2 over temperature, calibrated at 25c self calibration irq self calibration pass and fail signals are available as irq events. use register 0x01f[7:6] to enable these signals, and then use register 0x023[7:6] to read back their statuses and reset the irq signals. see the interrupt request operation section for more information.
ad9144 data sheet rev. a | page 82 of 125 device power dissipation the ad9144 has eight supply rails, avdd33, dvdd12, svdd12, siovdd33, cvdd12, iovdd, v tt , and pvdd12, which can be driven from five regulators to achieve optimum performance, as shown in figure 63. the avdd33 supply powers the dac core circuitry. the power dissipation of the avdd33 supply rail is independent of the digital operating mode and sample rate. the current drawn from the avdd33 supply rail is typically 126 ma (416 mw) when the full-scale current of dac0 to dac3 are set to the nominal value of 20.48 ma. pvdd12 powers the dac plls and varies depending on the dac sample rate. cvdd12 can be combined with the pvdd12 regulator but requires proper bypass capacitor networks near the pins. cvdd12 powers the clock tree, and the current varies directly with the dac sample rate. dvdd12 powers the dsp core, and the current draw depends on the number of dsp functions and the dac sample rate used. svdd12 supplies the serdes lanes and associated circuitry including the equalizers, serdes pll, phy, and up to the input of the dsp. the current depends on the number lanes and the lane bit rate. iovdd powers the spi circuit and draws very small current. siovdd33 powers the equalizers for the serdes lanes. the v tt termination voltage draws a very small current of <5 ma. temperature sensor the ad9144 has a band gap temperature sensor for monitoring the temperature changes of the ad9144 . the temperature must be calibrated against a known temperature to remove the device-to-device variation on the band gap circuit used to sense the temperature. to monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration of each ad9144 device. tx = t ref + 7.3 ( code_x ? code_ref )/1000 where: code_x is the readback code at the unknown temperature, tx . code_ref is the readback code at the calibrated temperature, t ref . to use the temperature sensor, it must be enabled by setting register 0x12f[0] to 1. the user mu st write a 1 to register 0x134[0] before reading back the die temperature from register 0x132 and register 0x133.
data sheet ad9144 rev. a | page 83 of 125 start-up sequence table 87 through table 96 show the register writes needed to set up the ad9144 with f dac = 1474.56 mhz, 2 interpolation, and the dac pll enabled with a 368.64 mhz reference clock. the jesd204b interface is configured in mode 4, dual-link mode, subclass 1, and scrambling is enabled with all eight serdes lanes running at 7.3728 gbps, inputting twos complement formatted data. no remapping of lanes with the crossbar is done in this example. the sequence of steps to properly start up the ad9144 are as follows: 1. set up the spi interface, power up necessary circuit blocks, make required writes to the configuration register, and set up the dac clocks (see the step 1: start up the dac section). 2. set the digital features of the ad9144 (see the step 2: digital datapath section). 3. set up the jesd204b links (see the step 3: transport layer section). 4. set up the physical layer of the serdes interface (see the step 4: physical layer section). 5. set up the data link layer of the serdes interface. this procedure is for quick startup or debug only and does not guarantee deterministic latency (see the step 5: data link layer section). 6. check for errors on link 0 and link 1 (see the step 6: error monitoring section). these steps are outlined in detail in the following sections in tables that list the required register write and read commands. step 1: start up the dac power-up and dac initialization table 87. power-up and dac initialization command address value description w 0x000 0xbd soft reset w 0x000 0x3c deassert reset, set 4-wire spi w 0x011 0x00 enable reference, dac channels, and master dac w 0x080 0x00 power up all clocks w 0x081 0x00 power up sysref receiver, disable hysteresis required device configurations table 88. required device configuration command address value description w 0x12d 0x8b digital datapath configuration w 0x146 0x01 digital datapath configuration w 0x2a4 0xff clock configuration w 0x232 0xff serdes interface configuration w 0x333 0x01 serdes interface configuration step 1a: configure the dac pll table 89. configure dac pll command address value description w 0x087 0x62 optimal dac pll loop filter settings w 0x088 0xc9 optimal dac pll loop filter settings w 0x089 0x0e optimal dac pll loop filter settings w 0x08a 0x12 optimal dac pll charge pump settings w 0x08d 0x7b optimal dac ldo settings for dac pll w 0x1b0 0x00 power dac pll blocks when power machine is disabled w 0x1b9 0x24 optimal dac pll charge pump settings w 0x1bc 0x0d optimal dac pll vco control settings w 0x1be 0x02 optimal dac pll vco power control settings w 0x1bf 0x8e optimal dac pll vco calibration settings w 0x1c0 0x2a optimal dac pll lock counter length setting w 0x1c1 0x2a optimal dac pll charge pump setting w 0x1c4 0x7e optimal dac pll varactor settings w 0x08b 0x02 set the vco lo divider to 8 so that 6 ghz f vco = f dacclk 2 (lodivmode + 1) 12 ghz w 0x08c 0x03 set the reference clock divider to 8 so that the reference clock into the pll is less than 80 mhz w 0x085 0x10 set the b counter to 16 to divide the dac clock down to 2 the reference clock w 0x1b5 0x09 pll lookup value from table 25 for f vco ? 7.25ghz w 0x1bb 0x13 pll lookup value from table 25 for f vco ? 7.25ghz w 0x1c5 0x06 pll lookup value from table 25 for f vco ? 7.25ghz w 0x083 0x10 enable dac pll r 0x084 0x01 verify that bit 1 reads back high for pll locked step 2: digital datapath table 90. digital datapath command address value description w 0x112 0x01 set the interpolation to 2 w 0x110 0x00 set twos complement data format
ad9144 data sheet rev. a | page 84 of 125 step 3: transport layer table 91. link 0 transport layer command address value description w 0x200 0x00 power up the interface w 0x201 0x00 enable all lanes w 0x300 0x08 bit 3 = 1 for dual-link, bit 2 = 0 to access link 0 registers w 0x450 0x00 set the device id to match tx (0x00 in this example) w 0x451 0x00 set the bank id to match tx (0x00 in this example) w 0x452 0x00 set the lane id to match tx (0x00 in this example) w 0x453 0x83 set descrambling and l = 4 (in n ? 1 notation) w 0x454 0x00 set f = 1 (in n ? 1 notation) w 0x455 0x1f set k = 32 (in n ? 1 notation) w 0x456 0x01 set m = 2 (in n ? 1 notation) w 0x457 0x0f set n = 16 (in n ? 1 notation) w 0x458 0x2f set subclass 1 and np = 16 (in n ? 1 notation) w 0x459 0x20 set jesd204b version and s = 1 (in n ? 1 notation) w 0x45a 0x80 set hd = 1 w 0x45d 0x45 set checksum for lane 0 w 0x46c 0x0f deskew lane 0 to lane 3 w 0x476 0x01 set f (not in n ? 1 notation) w 0x47d 0x0f enable lane 0 to lane 3 table 92. link 1 transport layer command address value description w 0x300 0x0c bit 3 = 1 for dual-link, bit 2 = 1 to access registers for link 1 w 0x450 0x00 set the device id to match tx (0x00 in this example) w 0x451 0x00 set the bank id to match tx (0x00 in this example) w 0x452 0x04 set the lane id to match tx (0x04 in this example) w 0x453 0x83 set descrambling and l = 4 (in n ? 1 notation) w 0x454 0x00 set f = 1 (in n ? 1 notation) w 0x455 0x1f set k = 32 (in n ? 1 notation) w 0x456 0x01 set m = 2 (in n ? 1 notation) w 0x457 0x0f set n = 16 (in n ? 1 notation) w 0x458 0x2f set subclass 1 and np = 16 (in n ? 1 notation) w 0x459 0x20 set jesd204b and s = 1 (in n ? 1 notation) w 0x45a 0x80 set hd w 0x45d 0x45 set checksum for lane 0 w 0x46c 0x0f deskew lane 4 to lane 7 w 0x476 0x01 set f (not in n ? 1 notation) w 0x47d 0x0f enable lane 4 to lane 7 step 4: physical layer table 93. physical layer command address value description w 0x2aa 0xb7 serdes interface termination setting w 0x2ab 0x87 serdes interface termination setting w 0x2b1 0xb7 serdes interface termination setting w 0x2b2 0x87 serdes interface termination setting w 0x2a7 0x01 autotune phy setting w 0x2ae 0x01 autotune phy setting w 0x314 0x01 serdes spi configuration w 0x230 0x28 configure cdrs in half rate mode w 0x206 0x00 resets cdr logic w 0x206 0x01 release cdr logic reset w 0x289 0x04 configure pll divider to 1 along with pll required configuration w 0x284 0x62 optimal serdes pll loop filter w 0x285 0xc9 optimal serdes pll loop filter w 0x286 0x0e optimal serdes pll loop filter w 0x287 0x12 optimal serdes pll charge pump w 0x28a 0x7b optimal serdes pll vco ldo w 0x28b 0x00 optimal serdes pll configuration w 0x290 0x89 optimal serdes pll vco varactor w 0x294 0x24 optimal serdes pll charge pump w 0x296 0x03 optimal serdes pll vco w 0x297 0x0d optimal serdes pll vco w 0x299 0x02 optimal serdes pll configuration w 0x29a 0x8e optimal serdes pll vco varactor w 0x29c 0x2a optimal serdes pll charge pump w 0x29f 0x78 optimal serdes pll vco varactor w 0x2a0 0x06 optimal serdes pll vco varactor w 0x280 0x01 enable serdes pll r 0x281 0x01 verify that bit 0 reads back high for serdes pll lock w 0x268 0x62 set eq mode to low power
data sheet ad9144 rev. a | page 85 of 125 step 5: data link layer note that this procedure does not guarantee deterministic latency. table 94. data link layerdoes not guarantee deterministic latency command address value description w 0x301 0x01 set subclass to 1 w 0x304 0x00 set the lmfc delay setting to 0 w 0x305 0x00 set the lmfc delay setting to 0 w 0x306 0x0a set the lmfc receive buffer delay to 10 w 0x307 0x0a set the lmfc receive buffer delay to 10 w 0x03a 0x01 set sync mode to one-shot sync w 0x03a 0x81 enable the sync machine w 0x03a 0xc1 arm the sync machine sysref signal ensure that at least one sysref edge is sent to the device w 0x300 0x0b bit 1 and bit 0 = 1 to enable link 0 and link 1, bit 2 = 0 to access link 0 step 6: error monitoring link 0 checks confirm that the registers in table 95 read back as noted and that system tasks are completed as described. table 95. link 0 checks command address value description r 0x470 0x0f acknowledge that four consecutive k28.5 characters have been detected on lane 0 to lane 3. syncout0 signal confirm that syncout0 is high. serdinx signals apply ilas and data to serdes input pins. r 0x471 0x0f check for frame sync on all lanes. r 0x472 0x0f check for good checksum. r 0x473 0x0f check for ilas. link 1 checks confirm that the registers in table 96 read back as noted and that system tasks are completed as described. table 96. link 1 checks command address value description w 0x300 0x0f bit 2 = 1 to access link 1. r 0x470 0x0f acknowledge that four consecutive k28.5 characters have been detected on lane 4 to lane 7. syncout0 signal confirm that syncout0 is high. serdinx signals apply ilas and data to serdes input pins. r 0x471 0x0f check for frame sync on all lanes. r 0x472 0x0f check for good checksum. r 0x473 0x0f check for ilas.
ad9144 data sheet rev. a | page 86 of 125 register maps and descriptions in the following tables, register addresses (reg. column) and rese t (reset column) values are hexadecimal, and in the read/writ e (r/w) column, r means read only, w means write only, r/w means read/write, and n/a means not applicable. all values in the register a ddress and reset columns are hexadecimal numbers. device configuration register map table 97. device configuration register map reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x000 spi_intfconfa soft reset_m lsbfirst_ m addrinc_m sdoactive_m sdoactive a ddrinc lsbfirst softreset 0x00 r/w 0x003 chiptype chiptype 0x04 r 0x004 prodidl prodidl 0x44 r 0x005 prodidh prodidh 0x91 r 0x006 chipgrade prod_grade dev_revision 0x06 r 0x008 spi_pageindx reserved dual_page 0x03 r/w 0x00a scratch_pad sc ratchpad 0x00 r/w 0x011 pwrcntrl0 pd_bg pd_dac_0 pd_dac_1 pd_da c_2 pd_dac_3 pd_dacm reserved 0x7c r/w 0x012 txenmask reserved dualb_ mask duala_ mask 0x00 r/w 0x013 pwrcntrl3 reserved pdp_ protect_ out tx_protect_ out reserved spi_protect_out spi_protect reserved 0x20 r/w 0x014 group_dly reserved group_dly 0x88 r/w 0x01f irqen_ statusmode0 irqen_ smode_ calpass irqen_ smode_ calfail irqen_ smode_ dacplllost irqen_smode _ dacplllock irqen_smode_ serplllost irqen_smode_ serplllock irqen_ smode_ lanefifoerr reserved 0x00 r/w 0x020 irqen_ statusmode1 reserved irqen_smode_ prbs3 irqen_smode_ prbs2 irqen_ smode_ prbs1 irqen_ smode_ prbs0 0x00 r/w 0x021 irqen_ statusmode2 irqen_ smode_ pdperr0 reserved irqen_ smode_ blnkdone0 irqen_smode _nco_align0 irqen_smode_ sync_lock0 irqen_smode_ sync_rotate0 irqen_ smode_ sync_ wlim0 irqen_ smode_ sync_trip0 0x00 r/w 0x022 irqen_ statusmode3 irqen_ smode_ pdperr1 reserved irqen_ smode_ blnkdone1 irqen_smode _nco_ align1 irqen_smode_ sync_lock1 irqen_ smode_sync_ rotate1 irqen_ smode_ sync_ wlim1 irqen_ smode_ sync_trip1 0x00 r/w 0x023 irq_status0 calpass calfail dacpll- lost dacplllock serplllost serplllock lanefifo- err reserved 0x00 r 0x024 irq_status1 reserved pr bs3 prbs2 prbs1 prbs0 0x00 r 0x025 irq_status2 pdperr0 reserved blnk- done0 nco_ align0 sync_ lock0 sync_ rotate0 sync_ wlim0 sync_ trip0 0x00 r 0x026 irq_status3 pdperr1 reserved blnk- done1 nco_ align1 sync_ lock1 sync_ rotate1 sync_ wlim1 sync_ trip1 0x00 r 0x030 jesd_checks rese rved err_dlyover err_winlim it err_jesdbad err_kunsupp err_ subclass err_ intsupp 0x00 r 0x034 sync_ errwindow reserved errwindow 0x00 r/w 0x038 sync_lasterr_l reserved lasterror 0x00 r 0x039 sync_lasterr_h lastun- der lastover reserved 0x00 r 0x03a sync_control sync- enable syncarm syncclr- stky syncclrlast syncmode 0x00 r/w 0x03b sync_status sync_ busy reserved sync_lock sync_ rotate sync_wlim sync_ trip 0x00 r 0x03c sync_currerr_l reserved currerror 0x00 r
data sheet ad9144 rev. a | page 87 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x03d sync_ currerr_h curr- under currover reserved 0x00 r 0x040 dacgain0_1 reserved dacfsc_0[9:8] 0x00 r/w 0x041 dacgain0_0 dacf sc_0[7:0] 0x00 r/w 0x042 dacgain1_1 reserved dacfsc_1[9:8] 0x00 r/w 0x043 dacgain1_0 dacf sc_1[7:0] 0x00 r/w 0x044 dacgain2_1 reserved dacfsc_2[9:8] 0x00 r/w 0x045 dacgain2_0 dacf sc_2[7:0] 0x00 r/w 0x046 dacgain3_1 reserved dacfsc_3[9:8] 0x00 r/w 0x047 dacgain3_0 dacf sc_3[7:0] 0x00 r/w 0x050 ncoalign_ mode nco_ align_ arm reserved nco_align_ mtch nco_align_ pass nco_align_fail reserved nco_align_mode 0x00 r/w 0x051 ncokey_ilsb ncok eyi[7:0] 0x00 r/w 0x052 ncokey_imsb ncok eyi[15:8] 0x00 r/w 0x053 ncokey_qlsb ncok eyq[7:0] 0x00 r/w 0x054 ncokey_qmsb ncok eyq[15:8] 0x00 r/w 0x060 pdp_thres0 pdp_thr eshold[7:0] 0x00 r/w 0x061 pdp_thres1 reserved pd p_threshold[12:8] 0x00 r/w 0x062 pdp_avg_time pdp_ enable reserved pdp_avg_time 0x00 r/w 0x063 pdp_power0 pdp_power[7:0] 0x00 r 0x064 pdp_power1 reserved pdp_power[12:8] 0x00 r 0x080 clkcfg0 pd_clk01 pd_clk23 pd_clk_dig pd_serdes_ pclk pd_clk_rec reserved 0xf8 r/w 0x081 sysref_actrl0 reserved pd_sysref hy s_on sysref_rise hys_cntrl1 0x10 r/w 0x082 sysref_actrl1 hys_cntrl0 0x00 r/w 0x083 dacpllcntrl recal_ dacpll reserved enable_ dacpll reserved 0x00 r/w 0x084 dacpllstatus dacpll_ over- range_h dacpll_ over- range_l dacpll_ cal_valid reserved dacpll_ lock reserved 0x00 r 0x085 dacinteger- word0 b_count 0x08 r/w 0x087 dacloopfilt1 lf_c2_word lf_c1_word 0x88 r/w 0x088 dacloopfilt2 lf_r1_word lf_c3_word 0x88 r/w 0x089 dacloopfilt3 lf_ bypass_ r3 lf_ bypass_r1 lf_bypass_ c2 lf_bypass_c1 lf_r3_word 0x08 r/w 0x08a daccpcntrl reserved cp_current 0x20 r/w 0x08b daclogencntrl reserv ed lo_div_mode 0x02 r/w 0x08c dacldocntrl1 reserved ref_div_mode 0x01 r/w 0x08d dacldocntrl2 dac_ldo 0x2b r/w 0x0e2 cal_ctrl_ global reserved cal_start_ avg cal_en_ avg 0x00 r/w 0x0e7 cal_clkdiv reserved cal_clk_en reserved 0x30 r/w 0x0e8 cal_page reserved cal_page 0x0f r/w 0x0e9 cal_ctrl cal_fin cal_ active cal_errhi cal_errlo reserved cal_start cal_en 0x00 r/w 0x0ed cal_init cal_init a6 r/w 0x110 data_format binary_ format reserved 00 r/w 0x111 datapath_ctrl invsinc_ enable reserved dig_gain_ enable phase_adj_ enable modulation_type sel_ sideband i_to_q 0xa0 r/w
ad9144 data sheet rev. a | page 88 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x112 interp_mode reserved interp _mode 0x01 r/w 0x113 nco_ftw_ update reserved ftw_update_ ack ftw_ update_ req 0x00 r/w 0x114 ftw0 ftw[7:0] 0x00 r/w 0x115 ftw1 ftw[15:8] 0x00 r/w 0x116 ftw2 ftw[23:16] 0x00 r/w 0x117 ftw3 ftw[31:24] 0x00 r/w 0x118 ftw4 ftw[39:32] 0x00 r/w 0x119 ftw5 ftw[47:40] 0x10 r/w 0x11a nco_phase_ offset0 nco_phase_offset[7:0] 0x00 r/w 0x11b nco_phase_ offset1 nco_phase_offset [15:8] 0x00 r/w 0x11c phase_adj0 phase_adj[7:0] 0x00 r/w 0x11d phase_adj1 reserved phase_adj[12:8] 0x00 r/w 0x11f txen_sm_0 fall_counters rise_counters reserved protect_out_ invert reserved 0x83 r/w 0x121 txen_rise_ count_0 rise_count_0 0x0f r/w 0x122 txen_rise_ count_1 rise_count_1 0x00 r/w 0x123 txen_fall_ count_0 fall_count_0 0xff r/w 0x124 txen_fall_ count_1 fall_count_1 0xff r/w 0x12d device_config_ reg_0 device_config_0 0x46 r/w 0x12f die_temp_ctrl0 reserved auxadc_ enable 0x20 r/w 0x132 die_temp0 die_temp[7:0] 0x00 r 0x133 die_temp1 die_temp[15:8] 0x00 r 0x134 die_temp_ update reserved die_temp_ update 0x00 r/w 0x135 dc_offset_ctrl reserved dc_offset_ on 0x00 r/w 0x136 ipath_dc_ offset_1part0 lsb_offset_i[7:0] 0x00 r/w 0x137 ipath_dc_ offset_1part1 lsb_offset_i[15:8] 0x00 r/w 0x138 qpath_dc_ offset_1part0 lsb_offset_q[7:0] 0x00 r/w 0x139 qpath_dc_ offset_1part1 lsb_offset_q[15:8] 0x00 r/w 0x13a ipath_dc_ offset_2part reserved sixteenth_offset_i 0x00 r/w 0x13b qpath_dc_ offset_2part reserved sixteenth_offset_q 0x00 r/w 0x13c idac_dig_gain0 idac_dig_gain[7:0] 0xea r/w 0x13d idac_dig_gain1 reserved idac_dig_gain[11:8] 0x0a r/w 0x13e qdac_dig_ gain0 qdac_dig_gain[7:0] 0xea r/w 0x13f qdac_dig_gain1 reserved qdac_dig_gain[11:8] 0x0a r/w 0x140 gain_ramp_up_ step0 gain_ramp_up_step[7:0] 0x04 r/w
data sheet ad9144 rev. a | page 89 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x141 gain_ramp_ up_step1 reserved gain_ramp_up_step[11:8] 0x00 r/w 0x142 gain_ramp_ down_step0 gain_ramp_down_step[7:0] 0x09 r/w 0x143 gain_ramp_ down_step1 reserved gain_ramp_do wn_step[11:8] 0x00 r/w 0x146 device_config_ reg_1 device_config_1 0x00 r/w 0x147 bsm_stat softblankrb reserved 0x00 r 0x14b prbs prbs_ good_q prbs_ good_i reserved prbs_mode prbs_reset prbs_en 0x10 r/w 0x14c prbs_error_i pr bs_count_i 0x00 r 0x14d prbs_error_q prbs_count_q 0x00 r 0x1b0 dacpllt0 dac_pll_pwr 0xfa r/w 0x1b5 dacpllt5 reserv ed vco_var 0x83 r/w 0x1b9 dacpllt9 dac_pll_cp1 0x34 r/w 0x1bb dacplltb reserved vco_bias_tcf vco_bias_ref 0x0c r/w 0x1bc dacplltc dac_pll_vco_ctrl 0x00 r/w 0x1be dacpllte dac_p ll_vco_pwr 0x00 r/w 0x1bf dacplltf dac_p ll_vcocal 0x8d r/w 0x1c0 dacpllt10 dac_p ll_lock_cntr 0x2e r/w 0x1c1 dacpllt11 dac_pll_cp2 0x24 r/w 0x1c4 dacpllt17 dac_pll_var1 0x33 r/w 0x1c5 dacpllt18 dac_pll_var2 0x08 r/w 0x200 master_pd reserved spi_pd_ master 0x01 r/w 0x201 phy_pd spi_pd_phy 0x00 r/w 0x203 generic_pd reserved spi_ sync1_pd spi_ sync2_pd 0x00 r/w 0x206 cdr_rese t reserved spi_cdr_ resetn 0x01 r/w 0x230 cdr_operating_ mode_reg_0 reserved enhalfrate reserved cdr_ oversamp reserved 0x28 r/w 0x232 device_config_ reg_3 device_config_3 0x0 r/w 0x268 eq_bias_reg eq_power_ mode reserved 0x62 r/w 0x280 serdespll_ enable_cntrl reserved recal_ serdespll reserved enable_ serdespll 0x00 r/w 0x281 pll_status reserved serdes_pll_ overrange_ h serdes_pll_ overrange_l serdes_pll_cal_ valid_rb reserved serdes_pll_ lock_rb 0x00 r 0x284 loop_filter_1 loop_filter_1 0x77 r/w 0x285 loop_filter_2 loop_filter_2 0x87 r/w 0x286 loop_filter_3 loop_filter_3 0x08 r/w 0x287 serdes_pll_cp1 serdes_pll_cp1 0x3f r/w 0x289 ref_clk_ divider_ldo reserved device_ config_4 serdes_pll_div_mode 0x00 r/w 0x28a vco_ldo serdes_pl l_vco_ldo 0x2b r/w 0x28b serdes_pll_pd1 serdes_pll_pd1 0x7f r/w 0x290 serdespll_va r1 serdes_pll_var1 0x83 r/w 0x294 serdes_pll_cp2 serde s_pll_cp2 0xb0 r/w 0x296 serdespll_vc o1 serdes_pll_vco1 0x0c r/w 0x297 serdespll_vco2 se rdes_pll_vco2 0x00 r/w
ad9144 data sheet rev. a | page 90 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x299 serdes_pll_pd2 serdes_pll_pd2 0x00 r/w 0x29a serdespll_var2 serdes_pll_var2 0xfe r/w 0x29c serdes_pll_cp3 se rdes_pll_cp3 0x17 r/w 0x29f serdespll_var3 serdes_pll_var3 0x33 r/w 0x2a0 serdespll_var4 se rdes_pll_var4 0x08 r/w 0x2a4 device_config_ reg_8 device_config_8 0x4b r/w 0x2a5 syncoutb_ swing reserved syncoutb_ swing_md 0x00 r/w 0x2a7 term_blk1_ ctrlreg0 reserved rcal_ termblk1 0x00 r/w 0x2aa device_config_ reg_9 device_config_9 0xc3 r/w 0x2ab device_config_ reg_10 device_config_10 0x93 r/w 0x2ae term_blk2_ ctrlreg0 reserved rcal_ termblk2 0x00 r/w 0x2b1 device_config_ reg_11 device_config_11 0xc3 r/w 0x2b2 device_config_ reg_12 device_config_12 0x93 r/w 0x300 general_jrx_ ctrl_0 reserved checksum _mode reserved link_mode link_page link_en 0x00 r/w 0x301 general_jrx_ ctrl_1 reserved subclassv_local 0x01 r/w 0x302 dyn_link_ latency_0 reserved dyn_link_latency_0 0x00 r 0x303 dyn_link_ latency_1 reserved dyn_link_latency_1 0x00 r 0x304 lmfc_delay_0 reserved lmfc_delay_0 0x00 r/w 0x305 lmfc_delay_1 reserved lmfc_delay_1 0x00 r/w 0x306 lmfc_var_0 reserved lmfc_var_0 0x06 r/w 0x307 lmfc_var_1 reserved lmfc_var_1 0x06 r/w 0x308 xbar_ln_0_1 reserved logical_lan e1_src logical_lane0_src 0x08 r/w 0x309 xbar_ln_2_3 reserved logical_lan e3_src logical_lan e2_src 0x1a r/w 0x30a xbar_ln_4_5 reserved logical_lan e5_src logical_lane4_src 0x2c r/w 0x30b xbar_ln_6_7 reserved logical_lan e7_src logical_lane6_src 0x3e r/w 0x30c fifo_status_ reg_0 lane_fifo_full 0x00 r 0x30d fifo_status_ reg_1 lane_fifo_empty 0x00 r 0x312 syncb_gen_1 rese rved syncb_err_dur reserved 0x00 r/w 0x314 serdes_spi_re g serdes_spi_co nfig 0x00 r/w 0x315 phy_prbs_test_ en phy_test_en 0x00 r/w 0x316 phy_prbs_test_ ctrl reserved phy_src_err_cnt phy_prbs_pat_sel phy_test_ start phy_test_ reset 0x00 r/w 0x317 phy_prbs_test_ threshold_ lobits phy_prbs_threshold[7:0] 0x00 r/w 0x318 phy_prbs_test_ threshold_ midbits phy_prbs_threshold[15:8] 0x00 r/w 0x319 phy_prbs_test_ threshold_ hibits phy_prbs_threshold[23:16] 0x00 r/w
data sheet ad9144 rev. a | page 91 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x31a phy_prbs_test_ errcnt_lobits phy_prbs_err_cnt[7:0] 0x00 r 0x31b phy_prbs_test_ errcnt_midbits phy_prbs_err_cnt[15:8] 0x00 r 0x31c phy_prbs_test_ errcnt_hibits phy_prbs_err_cnt[23:16] 0x00 r 0x31d phy_prbs_test_ status phy_prbs_pass 0xff r 0x32c short_tpl_ test_0 reserved short_ tpl_sp_sel shor t_tpl_dac_sel short_tpl_ test_reset short_tpl_ test_en 0x00 r/w 0x32d short_tpl_ test_1 short_tpl_ref_sp_lsb 0x00 r/w 0x32e short_tpl_ test_2 short_tpl_ref_sp _msb 0x00 r/w 0x32f short_tpl_ test_3 reserved short_ tpl_fail 0x00 r 0x333 device_config_ reg_13 device_config_13 0x00 r/w 0x334 jesd_bit_ inverse_ctrl jesd_bit_inverse 0x00 r/w 0x400 did_reg did_rd 0x00 r 0x401 bid_reg adjcnt_rd bid_rd 0x00 r 0x402 lid0_reg reserved adjd ir_rd phadj_rd lid0_rd 0x00 r 0x403 scr_l_reg sc r_rd reserved l-1_rd 0x00 r 0x404 f_reg f-1_rd 0x00 r 0x405 k_reg reserv ed k-1_rd 0x00 r 0x406 m_reg m-1_rd 0x00 r 0x407 cs_n_reg cs_rd re served n-1_rd 0x00 r 0x408 np_reg subclass v_rd np-1_rd 0x00 r 0x409 s_reg jesdv_ rd s-1_rd 0x00 r 0x40a hd_cf_reg hd_rd reserved cf_rd 0x00 r 0x40b res1_reg res1_rd 0x00 r 0x40c res2_reg res2_rd 0x00 r 0x40d checksum_reg fchk0_rd 0x00 r 0x40e compsum0_reg fcmp0_rd 0x00 r 0x412 lid1_reg reserved lid1_rd 0x00 r 0x415 checksum1_reg fchk1_rd 0x00 r 0x416 compsum1_reg fcmp1_rd 0x00 r 0x41a lid2_reg reserved lid2_rd 0x00 r 0x41d checksum2_reg fchk2_rd 0x00 r 0x41e compsum2_reg fcmp2_rd 0x00 r 0x422 lid3_reg reserved lid3_rd 0x00 r 0x425 checksum3_reg fchk3_rd 0x00 r 0x426 compsum3_reg fcmp3_rd 0x00 r 0x42a lid4_reg reserved lid4_rd 0x00 r 0x42d checksum4_reg fchk4_rd 0x00 r 0x42e compsum4_reg fcmp4_rd 0x00 r 0x432 lid5_reg reserved lid5_rd 0x00 r 0x435 checksum5_reg fchk5_rd 0x00 r 0x436 compsum5_reg fcmp5_rd 0x00 r 0x43a lid6_reg reserved lid6_rd 0x00 r 0x43d checksum6_reg fchk6_rd 0x00 r
ad9144 data sheet rev. a | page 92 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x43e compsum6_reg fcmp6_rd 0x00 r 0x442 lid7_reg reserved lid7_rd 0x00 r 0x445 checksum7_reg fchk7_rd 0x00 r 0x446 compsum7_reg fcmp7_rd 0x00 r 0x450 ils_did did 0x00 r/w 0x451 ils_bid adjcnt bid 0x00 r/w 0x452 ils_lid0 reserved adjdir phadj lid0 0x00 r/w 0x453 ils_scr_l scr re served l-1 0x83 r/w 0x454 ils_f f-1 0x00 r/w 0x455 ils_k reserved k-1 0x1f r/w 0x456 ils_m m-1 0x01 r/w 0x457 ils_cs_n cs rese rved n-1 0x0f r/w 0x458 ils_np subclass v np-1 0x2f r/w 0x459 ils_s jesdv s-1 0x20 r/w 0x45a ils_hd_cf hd reserved cf 0x80 r/w 0x45b ils_res1 res1 0x00 r/w 0x45c ils_res2 res2 0x00 r/w 0x45d ils_checksum fchk0 0x45 r/w 0x46b errcntrmon_rb readerrorcntr 0x00 r 0x46b errcntrmon reserved lanesel reserved cntrsel 0x00 r/w 0x46c lanedeskew la nedeskew 0x0f r/w 0x46d baddisparity_rb baddis 0x00 r 0x46d baddisparity rst_irq_ dis disable_ err_cntr_ dis rst_err_ cntr_dis reserved lane_addr_dis 0x00 r/w 0x46e nit_rb nit 0x00 r 0x46e nit_w rst_irq_ nit disable_ err_cntr_ nit rst_err_ cntr_nit reserved lane_addr_nit 0x00 r/w 0x46f unexpected- control_rb ucc 0x00 r 0x46f unexpected- control_w rst_irq_ ucc disable_ err_cntr_ ucc rst_err_ cntr_ucc reserved lane_addr_ucc 0x00 r/w 0x470 codegrpsyncflg codegrpsync 0x00 r/w 0x471 framesyncflg framesync 0x00 r/w 0x472 goodchksumflg goodchecksum 0x00 r/w 0x473 initlanesyncflg initiallanesync 0x00 r/w 0x476 ctrlreg1 f 0x01 r/w 0x477 ctrlreg2 ilas_ mode reserved threshold_ mask_en reserved 0x00 r/w 0x478 kval ksync 0x01 r/w 0x47a irqvector_mask baddis_ mask nit_mask ucc_ mask reserved initiallanesync_ mask badcheck sum_mask framesync_ mask codegrp sync_mask 0x00 r/w 0x47a irqvector_flag baddis_ flag nit_flag ucc_flag reserved initiallanesync_ flag badchecksum _flag framesync_ flag codegrp sync_flag 0x00 r 0x47b syncassertion- mask baddis_s nit_s ucc_ s cmm cmm_enable reserved 0x008 r/w 0x47c errorthres eth 0xff r/w 0x47d laneenable lane_ena 0x0f r/w 0x47e ramp_ena reserved ena_ramp_ check 0x00 r/w
data sheet ad9144 rev. a | page 93 of 125 reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x520 dig_test0 reserved dc_test_ mode reserved 0x1c r/w 0x521 dc_test_valuei0 dc_test_valuei[7:0] 0x00 r/w 0x522 dc_test_valuei1 dc_test_valuei[15:8] 0x00 r/w 0x523 dc_test_ valueq0 dc_test_valueq[7:0] 0x00 r/w 0x524 dc_test_ valueq1 dc_test_valueq[15:8] 0x00 r/w
ad9144 data sheet rev. a | page 94 of 125 device configuration re gister descriptions table 98. device configuration register descriptions address name bit no. bit name settings description reset access 0x000 spi_intfconfa 7 softreset_m soft reset (mirror). 0x0 r 6 lsbfirst_m lsb first (mirror). 0x0 r 5 addrinc_m address increment (mirror). 0x0 r 4 sdoactive_m sdo active (mirror). 0x0 r 3 sdoactive sdo active. 0x0 r/w 2 addrinc address increment. controls whether addresses are incremented or decremented during multibyte data transfers. 0x0 r/w 1 addresses are incremented during multibyte data transfers 0 addresses are decremented during multibyte data transfers 1 lsbfirst lsb first. controls whether input and output data are oriented as lsb first or msb first. 0x0 r/w 1 shift lsb in first 0 shift msb in first 0 softreset soft reset. setting this bit initiates a reset. this bit is autoclearing after the soft reset is complete. 0x0 r/w 1 assert soft reset 0x003 chiptype [7:0] chiptype the pr oduct type is high speed dac, which is represented by a code of 0x04. 0x4 r 0x004 prodidl [7:0] prodidl product identification low. 0x44 r 0x005 prodidh [7:0] prodidh product identification high. 0x91 r 0x006 chipgrade [7:4] prod_grade product grade. 0x0 r [3:0] dev_revision device revision. 0x6 r 0x008 spi_pageindx [7:2] re served reserved. 0x0 r [1:0] dual_page dual paging. selects which dual dac pair is accessed and written to when changing digital features, such as digital gain, dc offset, nco ftw, and others. this paging affects register 0x013 to register 0x014, register 0x034 to register 0x03d, register 0x050 to register 0x064, register 0x110 to register 0x124, and register 0x135 to register 0x14d. 0x3 r/w 0b01 read and write dual a 0b10 read and write dual b 0b11 write both duals; read dual a 0x00a scratch_pad [7:0] scratchpad this re gister does not affect any functions in the device and can be used for testing spi communication with the part. any value written to this register will be read back to reflect the change unless a reset or power- cycle occurs. 0x00 r/w 0x011 pwrcntrl0 7 pd_bg referenc e power-down. powers down the band gap reference for the entire chip. circuits will not be provided with bias currents. 0x0 r/w 1 power down reference 6 pd_dac_0 powers down dac0. powers down the i- channel dac of dual a. 0x1 r/w 1 powers down dac0 5 pd_dac_1 powers down dac1. powers down the q- channel dac of dual a. 0x1 r/w 1 powers down dac 1
data sheet ad9144 rev. a | page 95 of 125 address name bit no. bit name settings description reset access 4 pd_dac_2 powers down dac2. powers down the i- channel dac of dual b. 0x1 r/w 1 powers down dac 2 3 pd_dac_3 powers down dac3. powers down the q- channel dac of dual b. 0x1 r/w 1 powers down dac 3 2 pd_dacm powers down the dac master bias. the master bias cell provides currents and dac full-scale adjustments to the four dacs. with the dac master bias powered down, the dacs are inoperative. 0x1 r/w 1 powers down the dac master bias [1:0] reserved reserved. 0x0 r 0x012 txenmask [7:2] rese rved reserved. 0x0 r 1 dualb_mask dual b txen1 mask. power down dual b on a falling edge of txen1. 0x0 r/w 1 if txen1 is low, power down dac2 and dac3 0 duala_mask dual a txen0 mask. power down dual a on a falling edge of txen0. 0x0 r/w 1 if txen0 is low, power down dac0 and dac1 0x013 pwrcntrl3 7 reserv ed reserved. 0x0 r 6 pdp_protect_ out 1 pdp_protect triggers protect_outx. 0x0 r/w 5 tx_protect_out 1 tx_protect triggers protect_outx. 0x1 r/w 4 reserved reserved. 0x0 r 3 spi_protect_ out 1 spi_protect triggers protect_outx. 0x0 r/w 2 spi_protect spi_protect 0x0 r/w [1:0] reserved reserved. 0x0 r 0x014 group_dly [7:4] rese rved reserved. 0x8 r [3:0] group_dly group delay control. delays the i and q channel outputs together. 0 = minimum delay. 15 = maximum delay. the range of the delay is ?4 to +3.5 dac clock periods, and the resolution is 1/2 dac clock period. 0x8 r/w 0x01f irqen_ statusmode0 7 irqen_smode_ calpass calibration pass detection status mode. 0x0 r/w 1 if calpass goes high, it latches and pulls irq low 0 calpass shows current status 6 irqen_smode_ calfail calibration fail detection status mode. 0x0 r/w 1 if calfail goes high, it latches and pulls irq low 0 calfail shows current status 5 irqen_smode_ dacplllost dac pll lost detection status mode. 0x0 r/w 1 if dacplllost goes high, it latches and pulls irq low 0 dacplllost shows current status 4 irqen_smode_ dacplllock dac pll lock detection status mode. 0x0 r/w 1 if dacplllock goes high, it latches and pulls irq low 0 dacplllock shows current status 3 irqen_smode_ serplllost serdes pll lost detection status mode. 0x0 r/w 1 if serplllost goes high, it latches and pulls irq low 0 serplllost shows current status
ad9144 data sheet rev. a | page 96 of 125 address name bit no. bit name settings description reset access 2 irqen_smode_ serplllock serdes pll lock detection status mode. 0x0 r/w 1 if serplllock goes high, it latches and pulls irq low 0 serplllock shows current status 1 irqen_smode_ lanefifoerr lane fifo error detection status mode. 0x0 r/w 1 if lanefifoerr goes high, latches and pulls irq low 0 lanefifoerr shows current status 0 reserved reserved. 0x0 r 0x020 irqen_ statusmode1 [7:4] reserved reserved. 0x0 r 3 irqen_smode_ prbs3 dac3 prbs error status mode. 0x0 r/w 1 if prbs3 goes high, it latches and pulls irq low 0 prbs3 shows current status 2 irqen_smode_ prbs2 dac2 prbs error status mode. 0x0 r/w 1 if prbs2 goes high, it latches and pulls irq low 0 prbs2 shows current status 1 irqen_smode_ prbs1 dac1 prbs error status mode. 0x0 r/w 1 if prbs1 goes high, it latches and pulls irq low 0 prbs1 shows current status 0 irqen_smode_ prbs0 dac0 prbs error status mode. 0x0 r/w 1 if prbs0 goes high, it latches and pulls irq low 0 prbs0 shows current status 0x021 irqen_ statusmode2 7 irqen_smode_ pdperr0 dual a pdp error. 0x0 r/w 1 if pdperr0 goes high, it latches and pulls irq low 0 pdperr0 shows current status 6 reserved reserved. 0x0 r 5 irqen_smode_ blnkdone0 dual a blanking done status mode. 0x0 r/w 1 if blnkdone0 goes high, it latches and pulls irq low 0 blnkdone0 shows current status 4 irqen_smode_ nco_align0 dual a nco align tripped status mode 0x0 r/w 1 if nco_align0 goes high, it latches and pulls irq low 0 nco_align0 shows current status 3 irqen_smode_ sync_lock0 dual a alignment locked status mode. 0x0 r/w 1 if sync_lock0 goes high, it latches and pulls irq low 0 sync_lock0 shows current status 2 irqen_smode_ sync_rotate0 dual a alignment rotate status mode. 0x0 r/w 1 if sync_rotate0 goes high, it latches and pulls irq low 0 sync_rotate0 shows current status 1 irqen_smode_ sync_wlim0 dual a outside window status mode. 0x0 r/w 1 if sync_wlim0 goes high, it latches and pulls irq low 0 sync_wlim0 shows current status 0 irqen_smode_ sync_trip0 dual a alignment tripped status mode. 0x0 r/w 1 if sync_trip0 goes high, it latches and pulls irq low 0 sync_trip0 shows current status
data sheet ad9144 rev. a | page 97 of 125 address name bit no. bit name settings description reset access 0x022 irqen_ statusmode3 7 irqen_smode_ pdperr1 dual b pdp error. 0x0 r/w 1 if pdperr1 goes high, it latches and pulls irq low 0 pdperr1 shows current status 6 reserved reserved. 0x0 r 5 irqen_smode_ blnkdone1 dual b blanking done status mode. 0x0 r/w 1 if blnkdone1 goes high, it latches and pulls irq low 0 blnkdone1 shows current status 4 irqen_smode_ nco_align1 dual b nco align tripped status mode 0x0 r/w 1 if nco_align1 goes high, it latches and pulls irq low 0 nco_align1 shows current status 3 irqen_smode_ sync_lock1 dual b alignment locked status mode. 0x0 r/w 1 if sync_lock1 goes high, it latches and pulls irq low 0 sync_lock1 shows current status 2 irqen_smode_ sync_rotate1 dual b alignment rotate status mode. 0x0 r/w 1 if sync_rotate1 goes high, it latches and pulls irq low 0 sync_rotate1 shows current status 1 irqen_smode_ sync_wlim1 dual b outside window status mode. 0x0 r/w 1 if sync_wlim1 goes high, it latches and pulls irq low 0 sync_wlim1 shows current status 0 irqen_smode_ sync_trip1 dual b alignment tripped status mode. 0x0 r/w 1 if sync_trip1 goes high, it latches and pulls irq low 0 sync_trip1 shows current status 0x023 irq_status0 7 calpass calibration pass status. if irqen_smode_calpass is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 calibration passed 6 calfail calibration fail detection status. if irqen_smode_calfail is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 calibration failed 5 dacplllost dac pll lost status. if irqen_smode_dacplllost is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac pll lock was lost 4 dacplllock dac pll lock status. if irqen_smode_dacplllock is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac pll locked 3 serplllost serdes pll lost status. if irqen_smode_serplllost is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 serdes pll lock was lost
ad9144 data sheet rev. a | page 98 of 125 address name bit no. bit name settings description reset access 2 serplllock serdes pll lock status. if irqen_smode_serplllock is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 serdes pll locked 1 lanefifoerr lane fifo error status. if irqen_smode_lanefifoerr is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. a lane fifo error occurs when there is a full or empty condition on any of the fifos between the deserializer block and the core digital. this error requires a link disable and reenable to remove it. the status of the lane fifos can be found in register 0x30c (fifo full), and register 0x30d (fifo empty). 0x0 r 1 lane fifo error 0 reserved reserved. 0x0 r 0x024 irq_status1 [7:4] re served reserved. 0x0 r 3 prbs3 dac3 prbs error status. if irqen_smode_prbs3 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac3 failed prbs 2 prbs2 dac2 prbs error status. if irqen_smode_prbs2 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac2 failed prbs 1 prbs1 dac1 prbs error status. if irqen_smode_prbs1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac1 failed prbs 0 prbs0 dac0 prbs error status. if irqen_smode_prbs0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dac0 failed prbs 0x025 irq_status2 7 pdperr0 dual a pdp error. if irqen_smode_paerr0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 data into dual a over power threshold 6 reserved reserved. 0x0 r 5 blnkdone0 dual a blanking done status. if irqen_smode_blnkdone0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a blanking done 4 nco_align0 dual a nco align tripped status. if irqen_smode_nco_align0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a nco align tripped
data sheet ad9144 rev. a | page 99 of 125 address name bit no. bit name settings description reset access 3 sync_lock0 dual a lmfc alignment locked status. if irqen_smode_sync_lock0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a lmfc alignment locked 2 sync_rotate0 dual a lmfc alignment rotate status. if irqen_smode_sync_rotate0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a lmfc alignment rotated 1 sync_wlim0 dual a outside window status. if irqen_smode_sync_wlim0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a lmfc phase outside of window 0 sync_trip0 dual a lmfc alignment tripped status. if irqen_smode_sync_trip0 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual a lmfc alignment tripped 0x026 irq_status3 7 pdperr1 dual b pdp error. if irq_smode_pdperr1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 data into dual b over power threshold 6 reserved reserved. 0x0 r 5 blnkdone1 dual b blanking done status. if irqen_smode_blnkdone1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b blanking done 4 nco_align1 dual b nco align tripped status. if irqen_smode_nco_align1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b nco align tripped 3 sync_lock1 dual b lmfc alignment locked status. if irqen_smode_sync_lock1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b lmfc alignment locked 2 sync_rotate1 dual b lmfc alignment rotate status. if irqen_smode_sync_rotate1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b lmfc alignment rotated 1 sync_wlim1 dual b outside window status. if irqen_smode_sync_wlim1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b lmfc phase outside of window
ad9144 data sheet rev. a | page 100 of 125 address name bit no. bit name settings description reset access 0 sync_trip1 dual b lmfc alignment tripped status. if irqen_smode_sync_trip1 is low, this bit shows current status. if not, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. 0x0 r 1 dual b lmfc alignment tripped 0x030 jesd_checks [7:6] re served reserved. 0x0 r 5 err_dlyover error: lmfc_d elay > jesd_k parameter. 0x0 r 1 lmfc_delay > jesd_k 4 err_winlimit unsupported window limit. 0x0 r 1 unsupported sysref window limit 3 err_jesdbad unsupported m/l/s/f selection. 0x0 r 1 this jesd combination is not supported 2 err_kunsupp unsupported k values. 16 and 32 are supported. 0x0 r 1 k value unsupported 1 err_subclass unsupporte d subclass value. 0 and 1 are supported. 0x0 r 1 unsupported subclass value 0 err_intsupp unsupported interpolation rate factor. 1, 2, 4, 8 are supported. 0x0 r 1 unsupported interpolation rate factor 0x034 sync_errwindo w [7:2] reserved reserved. 0x0 r [1:0] errwindow lmfc sync error window. the error window allows the sysref sample phase to vary within the confines of the window without triggering a clock adjustment. this is useful if sysref cannot be guaranteed to always arrive in the same period of the device clock associated with the target phase. error window tolerance = errwindow 0x0 r/w 0x038 sync_lasterr_l [7:4] reserved reserved. 0x0 r [3:0] lasterror lmfc sync last alignment error. 4-bit twos complement value that represents the phase error (in number of dac clock cycles) when the clocks were last adjusted. r 0x039 sync_lasterr_h 7 lastunder lmfc sync last error under flag. 0x0 r 1 last phase error was beyond lower window tolerance boundary 6 lastover lmfc sync last error over flag. 0x0 r 1 last phase error was beyond upper window tolerance boundary [5:0] reserved reserved. 0x0 r 0x03a sync_control 7 syncenable lmfc sync logic enable. 0x0 r/w 1 enable sync logic 0 disable sync logic 6 syncarm lmfc sync arming strobe. 0x0 r/w 1 sync one-shot armed 5 syncclrstky lmfc sync sticky bit clear. on a rising edge, this bit clears sync_rotate and sync_trip. 0x0 r/w 4 syncclrlast lmfc sync clear last error. on a rising edge, this bit clears lasterror, lastunder, lastover. 0x0 r/w [3:0] syncmode lm fc sync mode. 0x0 r/w 0b0001 sync one-shot mode 0b0010 sync continuous mode 0b1000 sync monitor only mode 0b1001 sync one-shot, then monitor
data sheet ad9144 rev. a | page 101 of 125 address name bit no. bit name settings description reset access 0x03b sync_status 7 sync_busy lmfc sync machine busy. 0x0 r 1 sync logic sm is busy [6:4] reserved reserved. 0x0 r 3 sync_lock lmfc sync alignment locked. 0x0 r 1 sync logic aligned within window 2 sync_rotate lmfc sync rotated. 0x0 r 1 sync logic rotated with sysref (sticky) 1 sync_wlim lmfc sync alignment limit range. 0x0 r 1 phase error outside window threshold 0 sync_trip lmfc sync tripped after arming. 0x0 r 1 sync received sysref pulse (sticky) 0x03c sync_currerr_l [7:4] re served reserved. 0x0 r [3:0] currerror lmfc sync alignment error. 4-bit twos complement value that represents the phase error in number of dac clock cycles (that is, number of dac clocks between lmfc edge and sysref edge). when an adjustment of the clocks is made on any given sysref, the value of the phase error is placed into sync_ lasterr, and sync_currerr is forced to 0. 0x0 r 0x03d sync_currerr_h 7 currunder lmfc sync current error under flag. 0x0 r 1 current phase error is beyond lower window tolerance boundary 6 currover lmfc sync current error over flag. 0x0 r 1 current phase error is beyond upper window tolerance boundary [5:0] reserved reserved. 0x0 r 0x040 dacgain0_1 [7:2] re served reserved. 0x0 r [1:0] dacfsc_0[9:8] 2 msbs of i-channel dac gain dual a. a 10- bit twos complement value that is mapped to analog full-scale current for dac 0 as shown: 0x0 r/w 01111111111 = 27.0 ma 0000000000 = 20.48 ma 1000000000 = 13.9 ma 0x041 dacgain0_0 [7:0] dacfsc_0[7:0] 8 lsbs of i-channel dac gain dual a. 0x0 r/w 0x042 dacgain1_1 [7:2] re served reserved. 0x0 r [1:0] dacfsc_1[9:8] 2 msbs of q-channel dac gain dual a. a 10- bit twos complement value that is mapped to analog full-scale current for dac 1 as shown in register 0x040. 0x0 r/w 01111111111 = 27.0 ma 0000000000 = 20.48 ma 1000000000 = 13.9 ma 0x043 dacgain1_0 [7:0] dacfsc_1[7:0] 8 lsbs of q-channel dac gain dual a. 0x0 r/w 0x044 dacgain2_1 [7:2] re served reserved. 0x0 r [1:0] dacfsc_2[9:8] 2 msbs of i-channel dac gain dual b. a 10- bit twos complement value that is mapped to analog full-scale current for dac as shown in register 0x040. 0x0 r/w 01111111111 = 27.0 ma 0000000000 = 20.48 ma 1000000000 = 13.9 ma 0x045 dacgain2_0 [7:0] dacfsc_2[7:0] 8 lsbs of i-channel dac gain dual b. 0x0 r/w
ad9144 data sheet rev. a | page 102 of 125 address name bit no. bit name settings description reset access 0x046 dacgain3_1 [7:2] re served reserved. 0x0 r [1:0] dacfsc_3[9:8] 2 msbs of q-channel dac gain dual b. a 10- bit twos complement value that is mapped to analog full-scale current for dac 3 as shown in register 0x40. 0x0 r/w 01111111111 = 27.0 ma 0000000000 = 20.48 ma 1000000000 = 13.9 ma 0x047 dacgain3_0 [7:0] dacfsc_3[7:0] 8 lsbs of q-channel dac gain dual b. 0x0 r/w 0x050 ncoalign_mode 7 nco_align_arm ar m nco align. on a rising edge, arms the nco align operation. 0x0 r/w 6 reserved reserved. 0x0 r 5 nco_align_ mtch nco align data match. 0x0 r 1 key nco align data match 0 if finished, nco not aligned on data match 4 nco_align_pass nco align pass. 0x0 r 1 nco align takes effect 0 clear not taken effect yet 3 nco_align_fail nco align fail. 0x0 r 1 nco reset during rotate 0 not finished yet 2 reserved reserved. 0x0 r [1:0] nco_align_ mode nco align mode. 0x0 r/w 00 nco align disabled 10 nco align on data key 01 nco align on sysref 0x051 ncokey_ilsb [7:0] ncokeyi[7:0] nco data key for i channel. 0x0 r/w 0x052 ncokey_imsb [7:0] ncokeyi[15:8] nco data key for i channel. 0x0 r/w 0x053 ncokey_qlsb [7:0] ncokeyq[7:0] nco data key for q channel. 0x0 r/w 0x054 ncokey_qmsb [7:0] ncokeyq[15:8] nco data key for q channel. 0x0 r/w 0x060 pdp_thres0 [7:0] pdp_thres- hold[7:0] pdp_threshold is the average power threshold for comparison. if the moving average of signal power crosses this threshold, pdp_protect is set high. 0x0 r/w 0x061 pdp_thres1 [7:5] re served reserved. 0x0 r [4:0] pdp_ threshold[12:8] see register 0x60. 0x0 r/w 0x062 pdp_avg_time 7 pdp_enable 1 enab le average power calculation. 0x0 r/w [6:4] reserved reserved. 0x0 r [3:0] pdp_avg_time can be set from 0-10. averages across 2 (9 + pdp_avg_time) iq sample pairs. 0x0 r/w 0x063 pdp_power0 [7:0] pdp_power[7:0] if pdp_power has not gone over pdp_ threshold, pdp_power reads back the moving average of the signal power (i 2 + q 2 ). if pdp_threshold is crossed, pdp_power will hold the max value until its corresponding irq is cleared (0x025[7 or 0x026[7]). only 6 data msbs are used in calculating power. 0x0 r 0x064 pdp_power1 [7:5] re served reserved. 0x0 r [4:0] pdp_power[12:8] see register 0x063. 0x0 r
data sheet ad9144 rev. a | page 103 of 125 address name bit no. bit name settings description reset access 0x080 clkcfg0 7 pd_clk01 power-down clock for dual a. this bit disables the digital and analog clocks for dual a. 0x1 r/w 6 pd_clk23 power-down clock for dual b. this bit disables the digital and analog clocks for dual b. 0x1 r/w 5 pd_clk_dig power-down clocks to all dacs. this bit disables the digital and analog clocks for both duals. this includes all reference clocks, pclk, dac clocks, and digital clocks. 0x1 r/w 4 pd_serdes_pclk serdes pll clock power-down. this bit disables the reference clock to the serdes pll, which is needed to have an operational serial interface. 0x1 r/w 3 pd_clk_rec clock receiver power-down. this bit powers down the analog dac clock receiver block. with this bit set, clocks are not passed to internal nets. 0x1 r/w [2:0] reserved reserved. 0x0 r 0x081 sysref_actrl0 [7:5] re served reserved. 0x0 r 4 pd_sysref power-down sysref buffer. this bit powers down the sysref receiver. for subclass 1 operation to work, this buffer must be enabled. 0x1 r/w 3 hys_on hysteresis enabled. this bit enables the programmable hysteresis control for the sysref receiver. using hysteresis gives some noise resistance, but delays the sysref edge an amount depending on hys_cntrl and the sysref edge rate. the sysref kow is not guaranteed when using hysteresis. 0x0 r/w 2 sysref_rise select dac clock edge to sample sysref. 0x0 r/w 0 use falling edge of dac clock to sample sysref for alignment 1 use rising edge of dac clock to sample sysref for alignment [1:0] hys_cntrl1 hysteresis control bits[9:8]. hys_cntrl is a 10-bit thermometer-coded number. each bit set adds 10 mv of differential hysteresis to the sysref receiver. 0x0 r/w 0x082 sysref_actrl1 [7:0] hys_cntrl0 hy steresis control bits[7:0]. 0x0 r/w 0x083 dacpllcntrl 7 recal_dacpll recalibrate dac pll. on a rising edge of this bit, recalibrate the dac pll. 0x0 r/w [6:5] reserved reserved. 0x0 r 4 enable_dacpll synthesizer enable. this bit enables and calibrates the dac pll. 0x0 r/w [3:0] reserved reserved. 0x0 r 0x084 dacpllstatus 7 dacpll_ overrange_h dac pll high overrange. this bit indicates that the dac pll hit the upper edge of its operating band. recalibrate. 0x0 r 6 dacpll_ overrange_l dac pll low overrange. this bit indicates that the dac pll hit the lower edge of its operating band. recalibrate. 0x0 r 5 dacpll_cal_ valid dac pll calibration valid. this bit indicates that the dac pll has been successfully calibrated. 0x0 r [4:2] reserved reserved. 0x0 r 1 dacpll_lock dac pll lock bit. this bit is set high by the pll when it has achieved lock. 0x0 r 0 reserved reserved. 0x0 r
ad9144 data sheet rev. a | page 104 of 125 address name bit no. bit name settings description reset access 0x085 dacintegerword0 [7:0] b_count integer division word. this bit controls the integer feedback divider for the dac pll. determine the frequency of the dac clock by the following equations (see the dac pll fixed register writes section for more details): 0x8 r/w f dac = f ref /( ref_divrate ) 2 b_count f vco = f ref /( ref_divrate ) 2 b_count lo_div_mode minimum value is 6. 0x087 dacloopfilt1 [7:4] lf_c2_word c2 control word. set this control to 0x6 for optimal performance. 0x8 r/w [3:0] lf_c1_word c1 control word. set this control to 0x2 for optimal performance. 0x8 r/w 0x088 dacloopfilt2 [7:4] lf_r1_word r1 control word. set this control to 0xc for optimal performance. 0x8 r/w [3:0] lf_c3_word c3 control word. set this control to 0x9 for optimal performance. 0x8 r/w 0x089 dacloopfilt3 7 lf_bypass_r3 by pass r3 resistor. when this bit is set, bypass the r3 capacitor (set to 0 pf) when r3_word is set to 0. set this control to 0x0 for optimal performance. 0x0 r/w 6 lf_bypass_r1 bypass r1 resistor. when this bit is set, bypass the r1 capacitor (set to 0 pf) when r1_word is set to 0. set this control to 0x0 for optimal performance. 0x0 r/w 5 lf_bypass_c2 bypass c2 capacitor. when this bit is set, bypass the c2 capacitor (set to 0 pf) when c2_word is set to 0. set this control to 0x0 for optimal performance. 0x0 r/w 4 lf_bypass_c1 bypass c1 capacitor. when this bit is set, bypass the c1 capacitor (set to 0 pf) when c1_word is set to 0. set this control to 0x0 for optimal performance. 0x0 r/w [3:0] lf_r3_word r3 control word. set this control to 0xe for optimal performance. 0x8 r/w 0x08a daccpcntrl [7:6] rese rved reserved. 0x0 r [5:0] cp_current charge pump current control. set this control to 0x12 for optimal performance. 0x20 r/w 0x08b daclogencntrl [7:2] re served reserved. 0x0 r [1:0] lo_div_mode this range controls the rf clock divider between the vco and dac clock rates. the options are 4, 8, or 16 division. choose the lo_div_mode so that 6 ghz < f vco < 12 ghz (see the dac pll fixed register writes section for more details): 0x2 r/w 01 dac clock = vco/4 10 dac clock = vco/8 11 dac clock = vco/16
data sheet ad9144 rev. a | page 105 of 125 address name bit no. bit name settings description reset access 0x08c dacldocntrl1 [7:3] reserved reserved. 0x0 r [2:0] ref_div_mode referenc e clock division ratio. this field controls the amount of division that is done to the input clock at the clk+/clk? pins before it is presented to the pll as a reference clock. the reference clock frequency must be between 35 mhz and 80 mhz, but the clk+/clk? input frequency can range from 35 mhz to 1 ghz. the user sets this division to achieve a 35 mhz to 80 mhz pll reference frequency. for more details see the dac pll fixed register writes section. 0x1 r/w 000 1 001 2 010 4 011 8 100 16 0x08d dacldocntrl2 [7:0] dac_ldo dac pll ldo setting. this register must be written to 0x7b for optimal performance. 0x2b r/w 0x0e2 cal_ctrl_global [7:2] reserved reserved. 0x0 r 1 cal_start_avg averaged calibration start. on rising edge, calibrate the dacs. only use if calibrating all dacs. 0x0 r/w 0 cal_en_avg averaged calibration enable. set prior to starting calibration with cal_start_avg. while this bit is set, calibration can be performed, and the results are applied. 0x0 r/w 1 enable averaged calibration 0x0e7 cal_clkdiv [7:4] reserved must write the default value for proper operation. 0x3 r/w 3 cal_clk_en enable self calibration clock. 0x0 r/w 1 enable calibration clock 0 disable calibration clock [2:0] reserved reserved. 0x0 r 0x0e8 cal_page [7:4] rese rved reserved. 0x0 r [3:0] cal_page dac calibration paging. selects which of the dacs are being accessed for calibration or calibration readback. this paging affects register 0x0e9 and register 0x0ed. 0xf r/w calibration: any number of dacs can be accessed simultaneously to write and calibrate. write a 1 to bit x to include dac x. readback: only one dac at a time can be accessed when reading back cal_ctrl (register 0x0e9). write a 1 to bit x to read from dac x (the other bits must be 0). 0x0e9 cal_ctrl 7 cal_fin calibratio n finished. this bit is high when the calibration has completed. if the calibration completes and either cal_errhi or cal_ errlo is high, then the calibration cannot be considered valid and are considered a timeout event. 0x0 r 1 calibration ran and is finished 6 cal_active calibration active. this bit is high while the calibration is in progress. 0x0 r 1 calibration is running
ad9144 data sheet rev. a | page 106 of 125 address name bit no. bit name settings description reset access 5 cal_errhi sar data error: too high. this bit is set at the end of a calibration cycle if any of the calibra- tion dacs has overranged to the high side. this typically means that the algorithm adjusts the calibration preset of the calibration dacs and runs another cycle. 0x0 r 1 data saturated high 4 cal_errlo sar data error: too low. this bit is set at the end of a calibration cycle if any of the calibra- tion dacs has overranged to the low side. this typically means that the algorithm adjusts the calibration preset of the calibration dacs and runs another cycle. 0x0 r 1 data saturated low [3:2] reserved reserved. 0x0 r 1 cal_start calibration start. the rising edge of this bit kicks off a calibration sequence for the dacs that have been selected in the cal_indx register. 0x0 r/w 0 normal operation 1 start calibration state machine 0 cal_en calibration enable. enable the calibration dac of the converter. enable to calibration engine and machines. prepare for a calibration start. for calibration coefficients to be applied to the calibrated dacs, this bit must be high. 0x0 r/w 0 do not use calibration dacs 1 use calibration dacs 0x0ed cal_init [7:0] cal_init initialize calibration. must be written to 0xa2 before starting calibration or averaged calibration. 0xa6 r/w 0x110 data_format 7 binary_format bin ary or twos complementary format on the data bus. 0x0 r/w 0 input data is twos complement 1 input data is offset binary [6:0] reserved reserved. 0x0 r 0x111 datapath_ctrl 7 invsinc_enable enable inverse sinc filter. 0x1 r/w 1 enable inverse sinc filter 0 disable inverse sinc filter 6 reserved reserved. 0x0 r 5 dig_gain_enable enable digital gain. 0x1 r/w 1 enable digital gain function 0 disable digital gain function 4 phase_adj_ enable enable phase compensation. 0x0 r/w 1 enable phase adjust compensation 0 disable phase adjust compensation [3:2] modulation_type selects type of modulation operation. 0x0 r/w 00 no modulation 01 fine modulation (uses ftw) 10 f s /4 coarse modulation 11 f s /8 coarse modulation 1 sel_sideband spectrum inversion control. can only be used with fine modulation. this causes the negative sideband to be selected and is equivalent to changing the sign of ftw. 0x0 r/w 0 i_to_q send i data into q dac datapath. occurs at the end of the digital datapath prior to entering dacs. 0x0 r/w
data sheet ad9144 rev. a | page 107 of 125 address name bit no. bit name settings description reset access 0x112 interp_mode [7:3] re served reserved. 0x0 r [2:0] interp_mode in terpolation mode. 0x1 r/w 000 1 mode 001 2 mode 011 4 mode 100 8 mode 0x113 nco_ftw_update [7:2] reserved reserved. 0x0 r 1 ftw_update_ack frequency tuning word update acknowledge. this readback is high when an ftw has been updated. 0x0 r 0 ftw_update_req frequency tuning word update request from spi. unlike most registers, those relating to fine nco modulation (register 0x114 to register 0x11b) are not updated immediately upon writing to them. once the desired ftw and phase offset values are written, set this bit. these registers update on the rising edge of this bit. it is only after this update that the internal state matches register 0x114 to register 0x11b. confirmation that this update has occurred can be made by reading back bit 1 of this register and ensuring it is set high for the update acknowledge. 0x0 r/w 0x114 ftw0 [7:0] ftw[7:0] nco frequency tuning word. 0x0 r/w 0x115 ftw1 [7:0] ftw[15:8] nco frequency tuning word. 0x0 r/w 0x116 ftw2 [7:0] ftw[23:16] nco frequency tuning word. 0x0 r/w 0x117 ftw3 [7:0] ftw[31:24] nco frequency tuning word. 0x0 r/w 0x118 ftw4 [7:0] ftw[39:32] nco frequency tuning word. 0x0 r/w 0x119 ftw5 [7:0] ftw[47:40] nco frequency tuning word. 0x10 r/w 0x11a nco_phase_ offset0 [7:0] nco_phase_ offset[7:0] 8 lsbs of nco phase offset. nco_phase_offset changes the phase of both i and q data, and is only functional when using nco fine modulation. it is a 16- bit twos complement number ranging from ?180 to+180 degrees in steps of .0055. 0x0 r/w 0x11b nco_phase_ offset1 [7:0] nco_phase_ offset[15:8] 8 msbs of nco phase offset. 0x0 r/w 0x11c phase_adj0 [7:0] phase_adj[7:0] 8 lsbs of phase compensation word. phase compensation changes the phase between the i and q data. phase_adj is a 13-bit twos complement value. the control ranges from ?14 to +14 with 0.0035 resolution steps. 0x0 r/w 0x11d phase_adj1 [7:5] re served reserved. 0x0 r [4:0] phase_adj[12:8] 5 msbs of phase compensation word. 0x0 r/w 0x11f txen_sm_0 [7:6] fall_counters fall counters. the number of counters to use to delay tx_protect fall from txenx falling edge. must be set to 1 or 2. 0x2 r/w [5:4] rise_counters rise counters. the number of counters to use to delay tx_protect rise from txenx rising edge. 0x0 r/w 3 reserved reserved. 0x0 r 2 protect_out_ invert protect_outx invert. 0x0 r/w 0 protect_outx is high when output is valid. suitable for enabling downstream components during transmission 1 protect_outx is high when output is invalid. suitable for disabling downstream components when not transmitting [1:0] reserved must writ e the default value for proper operation. 0x3 r/w
ad9144 data sheet rev. a | page 108 of 125 address name bit no. bit name settings description reset access 0x121 txen_rise_ count_0 [7:0] rise_count_0 first counter used to delay tx_protect rise from txenx rising edge. delays by 32 rise_count_0 dac clock cycles. 0xf r/w 0x122 txen_rise_ count_1 [7:0] rise_count_1 second counter used to delay tx_protect rise from txenx rising edge. delays by 32 rise_count_1 dac clock cycles. 0x0 r/w 0x123 txen_fall_ count_0 [7:0] fall_count_0 first counter used to delay tx_protect fall from txenx falling edge. delays by 32 fall_count_0 dac clock cycles. must be set to a minimum of 0x12. 0xff r/w 0x124 txen_fall_ count_1 [7:0] fall_count_1 second counter used to delay tx_protect fall from txenx falling edge. delays by 32 fall_count_1 dac clock cycles. 0xff r/w 0x12d device_config_ reg_0 [7:0] device_config_0 must be set to 0x8b for proper digital datapath configuration. 0x46 r/w 0x12f die_temp_ctrl0 [7:1] reserved mu st write the default value for proper operation. 0x10 r/w 0 auxadc_enable enables the aux adc block. 0x0 r/w 0 aux adc disable 1 aux adc enable 0x132 die_temp0 [7:0] die_temp[7:0] aux adc readback value. 0x0 r 0x133 die_temp1 [7:0] die_temp[15:8] aux adc readback value. 0x0 r 0x134 die_temp_update [7:1] reserved reserved. 0x0 r 0 die_temp_ update die temperature update. on a rising edge, a new temperature code is generated. 0x0 r/w 0x135 dc_offset_ctrl [7:1] re served reserved. 0x0 r 0 dc_offset_on dc offset on. 0x0 r/w 1 enables dc offset module 0x136 ipath_dc_offset_ 1part0 [7:0] lsb_offset_i[7:0] 8 lsbs of ipath dc offset. lsb_offset_i is a 16-bit twos complement number that is added to incoming data. 0x0 r/w 0x137 ipath_dc_offset_ 1part1 [7:0] lsb_offset_i[15:8] 8 msbs of ipath dc offset. lsb_offset_i is a 16-bit twos complement number that is added to incoming i data. 0x0 r/w 0x138 qpath_dc_offset_ 1part0 [7:0] lsb_offset_ q[7:0] 8 lsbs of qpath dc offset. lsb_offset_q is a 16-bit twos complement number that is added to incoming q data. 0x0 r/w 0x139 qpath_dc_offset_ 1part1 [7:0] lsb_offset_ q[15:8] 8 msbs of qpath dc offset. lsb_offset_q is a 16-bit twos complement number that is added to incoming q data. 0x0 r/w 0x13a ipath_dc_offset_ 2part [7:5] reserved reserved. 0x0 r [4:0] sixteenth_ offset_i sixteenth_offset_i is a 5-bit twos complement number in 16ths of an lsb that is added to incoming i data. 0x0 r/w x x/16 lsb dc offset 0x13b qpath_dc_offset_ 2part [7:5] reserved reserved. 0x0 r [4:0] sixteenth_ offset_q sixteenth_offset_q is a 5-bit twos complement number in 16ths of an lsb that is added to incoming q data. 0x0 r/w x x/16 lsb dc offset 0x13c idac_dig_gain0 [7:0] idac_dig_ gain[7:0] 8 lsbs of i dac digital gain. idac_dig_gain is the digital gain of the idac. the digital gain is a multiplier from 0 to 4095/2048 in steps of 1/2048. 0xea r/w 0x13d idac_dig_gain1 [7:4] reserved reserved. 0x0 r [3:0] idac_dig_ gain[11:8] 4 msbs of i dac digital gain 0xa r/w
data sheet ad9144 rev. a | page 109 of 125 address name bit no. bit name settings description reset access 0x13e qdac_dig_gain0 [7:0] qdac_dig_ gain[7:0] 8 lsbs of q dac digital gain. qdac_dig_gain is the digital gain of the qdac. the digital gain is a multiplier from 0 to 4095/2048 in steps of 1/2048. 0xea r/w 0x13f qdac_dig_gain1 [7:4] reserved reserved. 0x0 r [3:0] qdac_dig_ gain[11:8] 4 msbs of q dac digital gain. 0xa r/w 0x140 gain_ramp_up_ step0 [7:0] gain_ramp_up_ step[7:0] 8 lsbs of gain ramp up step. gain_ramp_up_step controls the amplitude step size of the bsms ramping feature when the gain is being ramped to its assigned value. 0x4 r/w 0x0 smallest ramp up step size 0xfff largest ramp up step size 0x141 gain_ramp_up_ step1 [7:4] reserved reserved. 0x0 r [3:0] gain_ramp_up_ step[11:8] 4 msbs of gain ramp up step. see register 0x140 for description. 0x0 r/w 0x142 gain_ramp_down_ step0 [7:0] gain_ramp_ down_step[7:0] 8 lsbs of gain ramp down step. gain_ramp_down_step controls the amplitude step size of the bsms ramping feature when the gain is being ramped to zero. 0x9 r/w 0 smallest ramp down step size 0xfff largest ramp down step size 0x143 gain_ramp_ down_step1 [7:4] reserved reserved. 0x0 r [3:0] gain_ramp_ down_step[11:8] 4 msbs of gain ramp down step. see register 0x142 for description. 0x0 r/w 0x146 device_config_ reg_1 [7:0] device_config_1 must be set to 0x01 for proper digital datapath configuration. 0x0 r/w 0x147 bsm_stat [7:6] softblan krb blanking state. 0x0 r 00 data is fully blanked 01 ramping from data process to full blanking 10 ramping from fully blanked to data process 11 data is being processed [5:0] reserved reserved. 0x0 r 0x14b prbs 7 prbs_good_q good data indicator imaginary channel. 0x0 r 0 incorrect sequence detected 1 correct prbs sequence detected 6 prbs_good_i good data indicator real channel. 0x0 r 0 incorrect sequence detected 1 correct prbs sequence detected [5:3] reserved reserved. 0x0 r 2 prbs_mode polynomial select 0x0 r/w 0 7-bit: x 7 + x 6 + 1 1 15-bit: x 15 + x 14 + 1 1 prbs_reset reset error counters. 0x0 r/w 0 normal operation 1 reset counters 0 prbs_en enable prbs checker. 0x0 r/w 0 disable 1 enable 0x14c prbs_error_i [7:0] prbs_count_i error count value real channel. 0x0 r 0x14d prbs_error_q [7:0] prb s_count_q error count valu e imaginary channel. 0x0 r 0x1b0 dacpllt0 [7:0] dac_pll_pwr dac p ll pd settings. this register must be written to 0x00 for optimal performance. 0xfa r/w
ad9144 data sheet rev. a | page 110 of 125 address name bit no. bit name settings description reset access 0x1b5 dacpllt5 [7:4] reserved must write the default value for proper operation. 0x8 r/w [3:0] vco_var varactor kvo setting. see table 83 for optimal settings based on the f vco being used. 0x3 r/w 0x1b9 dacpllt9 [7:0] dac_pll_cp1 dac p ll charge pump settings. this register must be written to 0x24 for optimal performance. 0x34 r/w 0x1bb dacplltb [7:5] rese rved reserved. 0x0 r [4:3] vco_bias_tcf temperature coefficient for vco bias. see table 83 for optimal settings based on the f vco being used. 0x1 r/w [2:0] vco_bias_ref vco bias control. see table 83 for optimal settings based on the f vco being used. 0x4 r/w 0x1bc dacplltc [7:0] dac_pll_vco_ ctrl dac pll vco control settings. this register must be written to 0x0d for optimal performance. 0x00 r/w 0x1be dacpllte [7:0] dac_pll_vco_ pwr dac pll vco power control settings. this register must be written to 0x02 for optimal performance. 0x00 r/w 0x1bf dacplltf [7:0] dac_pll_vcocal dac pll vco calibration settings. this register must be written to 0x8e for optimal performance. 0x8d r/w 0x1c0 dacpllt10 [7:0] dac_pll_lock_ cntr this register must be written to 0x2a for optimal performance. 0x2e r/w 0x1c1 dacpllt11 [7:0] dac_pll_cp2 this register must be written to0x2a for optimal performance. 0x24 r/w 0x1c4 dacpllt17 [7:0] dac_pll_var1 da c pll varactor setting. must be set to 0x7e for proper dac pll configuration. 0x33 r/w 0x1c5 dacpllt18 [7:0] dac_pll_var2 dac pll varactor setting. see table 83 for optimal settings based on the f vco being used. 0x08 r/w 0x200 master_pd [7:1] rese rved reserved. 0x0 r 0 spi_pd_master power down the entire jesd receiver analog (all eight channels plus bias). 0x1 r/w 0x201 phy_pd [7:0] spi_pd_phy spi ov erride to power down the individual phys. 0x0 r/w set bit x to power down the corresponding serdinx phy 0x203 generic_pd [7:2] reserved reserved. 0x0 r 1 spi_sync1_pd power down lvds buffer for syncout0 . 0x0 r/w 0 spi_sync2_pd power down lvds buffer for syncout1 . 0x0 r/w 0x206 cdr_reset [7:1] rese rved reserved. 0x0 r 0 spi_cdr_resetn resets the digital control logic for all phys. 0x1 r/w 0 hold cdr in reset 1 enable cdr 0x230 cdr_operating_ mode_reg_0 [7:6] reserved reserved. 0x0 r 5 enhalfrate enables half-rate cdr operation. set to 1 when 5.75 gbps lane rate 10.64. 0x1 r/w [4:2] reserved must writ e the default value for proper operation. 0x2 r/w 1 cdr_oversamp enables oversampling of the input data. set to 1 when 1.44 gbps lane rate 2.76 gbps. 0x0 r/w 0 reserved reserved. 0x0 r 0x232 device_config_ reg_3 [7:0] device_config_3 must be set to 0xff for proper jesd interface configuration. 0x0 r/w
data sheet ad9144 rev. a | page 111 of 125 address name bit no. bit name settings description reset access 0x268 eq_bias_reg [7:6] eq_power_ mode control the equalizer power/insertion loss capability. 0x1 r/w 00 normal mode 01 low power mode [5:0] reserved must writ e the default value for proper operation. 0x22 r/w 0x280 serdespll_ enable_cntrl [7:3] reserved reserved. 0x0 r 2 recal_serdespll recalibrat e serdes pll. on a rising edge, recalibrate the serdes pll. 0x0 r/w 1 reserved reserved. 0x0 r 0 enable_ serdespll enable the serdes pll. setting this bit enables and calibrates the serdes pll. 0x0 r/w 0x281 pll_status [7:6] re served reserved. 0x0 r 5 serdes_pll_ overrange_h serdes pll high overrange. this bit indicates that the serdes pll hit the lower edge of its operating band. recalibrate. 0x0 r 4 serdes_pll_ overrange_l serdes pll low overrange. this bit indicates that the serdes pll hit the lower edge of its operating band. recalibrate. 0x0 r 3 serdes_pll_cal_ valid_rb serdes pll calibration valid. this bit indicates that the serdes pll has been successfully calibrated. 0x0 r [2:1] reserved reserved. 0x0 r 0 serdes_pll_ lock_rb serdes pll lock. this bit is set high by the pll when it has achieved lock. 0x0 r 0x284 loop_filter_1 [7:0] loop _filter_1 serdes pll loop filter setting. this register must be written to 0x62 for optimal performance. 0x77 r/w 0x285 loop_filter_2 [7:0] loop _filter_2 serdes pll loop filter setting. this register must be written to 0xc9 for optimal performance. 0x87 r/w 0x286 loop_filter_3 [7:0] loop _filter_3 serdes pll loop filter setting. this register must be written to 0x0e for optimal performance. 0x08 r/w 0x287 serdes_pll_cp1 [7:0] serdes_pll_cp1 serdes p ll charge pump setting. this register must be written to 0x12 for optimal performance. 0x3f r/w 0x289 ref_clk_divider_ ldo [7:3] reserved reserved. 0x0 r 2 device_config_4 must be set to 1 for proper serdes pll configuration. 0x0 r/w [1:0] serdes_pll_div_ mode serdes pll reference clock division factor. this field controls the division of the serdes pll reference clock before it is fed into the serdes pll phase frequency detector (pfd). it must be set so f ref /divfactor is between 35 mhz and 80 mhz. 0x0 r/w 00 divide by 4 for 5.75 gbps to 10.64 gbps lane rate 01 divide by 2 for 2.88 gbps to 5.52 gbps lane rate 10 divide by 1 for 1.44 gbps to 2.76 gbps lane rate 0x28a vco_ldo [7:0] serdes_pll_ vco_ldo serdes pll vco ldo setting. this register must be written to 0x7b for optimal performance. 0x2b r/w 0x28b serdes_pll_pd1 [7:0] serd es_pll_pd1 serdes pll pd se tting. this register must be written to 0x00 for optimal performance. 0x7f r/w 0x290 serdespll_var1 [7:0] serdes_pll_var1 serdes pll varactor setting. this register must be written to 0x89 for optimal performance. 0x83 r/w
ad9144 data sheet rev. a | page 112 of 125 address name bit no. bit name settings description reset access 0x294 serdes_pll_cp2 [7:0] serdes_pll_cp2 serdes p ll charge pump setting. this register must be set to 0x24 for optimal performance. 0xb0 r/w 0x296 serdespll_vco1 [7:0] serdes_pll_ vco1 serdes pll vco setting. this register must be set to 0x03 for optimal performance. 0x0c r/w 0x297 serdespll_vco2 [7:0] serdes_pll_ vco2 serdes pll vco setting. this register must be set to 0x0d for optimal performance. 0x00 r/w 0x299 serdes_pll_pd2 [7:0] serd es_pll_pd2 serdes pll pd se tting. this register must be set to 0x02 for optimal performance. 0x00 r/w 0x29a serdespll_var2 [7:0] se rdes_pll_var2 serdes pll varactor setting. this register must be set to 0x8e for optimal performance. 0xfe r/w 0x29c serdes_pll_cp3 [7:0] se rdes_pll_cp3 serdes pll ch arge pump setting. must be set to 0x2a for proper serdes pll configuration. 0x17 r/w 0x29f serdespll_var3 [7:0] serdes_pll_var3 serdes pll varactor setting. must be set to 0x78 for proper serdes pll configuration. 0x33 r/w 0x2a0 serdespll_var4 [7:0] serdes_pll_var4 serdes pll varactor setting. this register must be set to 0x06 for optimal performance. 0x08 r/w 0x2a4 device_config_ reg_8 [7:0] device_config_8 must be set to 0xff for proper clock configuration. 0x4b r/w 0x2a5 syncoutb_swing [7:1] re served reserved. 0x0 r 0 syncoutb_ swing_md syncoutx swing mode. sets the output differential swing mode for the syncoutx pins. see table 8 for details. 0x0 r/w 0 normal swing mode 1 high swing mode 0x2a7 term_blk1_ ctrlreg0 [7:1] reserved reserved. 0x0 r 0 rcal_termblk1 termination calibration. the rising edge of this bit calibrates phy0, phy1, phy6, and phy7 terminations to 5 0 . 0x0 r/w 0x2aa device_config_ reg_9 [7:0] device_config_ 9 must be set to 0xb7 for proper jesd interface termination configuration. 0xc3 r/w 0x2ab device_config_ reg_10 [7:0] device_config_ 10 must be set to 0x87 for proper jesd interface termination configuration. 0x93 r/w 0x2ae term_blk2_ ctrlreg0 [7:1] reserved reserved. 0x0 r 0 rcal_termblk2 terminal cali bration. the rising edge of this bit calibrates phy2, phy3, phy4 and phy5 terminations to 50 . 0x0 r/w 0x2b1 device_config_ reg_11 [7:0] device_config_ 11 must be set to 0xb7 for proper jesd interface termination configuration. 0xc3 r/w 0x2b2 device_config_ reg_12 [7:0] device_config_ 12 must be set to 0x87 for proper jesd interface termination configuration. 0x93 r/w 0x300 general_jrx_ ctrl_0 7 reserved reserved. 0x0 r 6 checksum_mode checksum mode. this bit controls the locally generated jesd204b link parameter checksum method. the value is stored in the fcmp registers (register 0x40e, register 0x416, register 0x41e, register 0x426, register 0x42e, register 0x436, register 0x43e, and register 0x446). 0x0 r/w 0 checksum is calculated by summing the individual fields in the link configuration table as defined in section 8.3, table 20 of the jesd204b standard 1 checksum is calculated by summing the regis- ters containing the packed link configuration fields ([0x450:0x45a] modulo 256). [5:4] reserved reserved. 0x0 r
data sheet ad9144 rev. a | page 113 of 125 address name bit no. bit name settings description reset access 3 link_mode link mode. this register selects either single- link or dual-link mode. 0x0 r/w 0 single-link mode 1 dual-link mode 2 link_page link paging. se lects which links register map is used. this paging affects registers 0x401 to 0x47e. 0x0 r/w 0 use link 0 register map 1 use link 1 register map [1:0] link_en link enable. these bits bring up the jesd204b receiver digital circuitry: bit 0 for link 0 and bit 1 for link 1. enable the link only after the following has occurred: all jesd204b para- meters are set, the dac pll is enabled and locked (register 0x084[1] = 1), and the jesd204b phy is enabled (register 0x200 = 0x00) and calibrated (register 0x281[2] = 0). 0x0 r/w 0b00 disable both jesd link 1 and jesd link 0 0b01 disable jesd link 1, enable jesd link 0 0b10 enable jesd link 1, disable jesd link 0 0b11 enable both jesd link 1 and jesd link 0 0x301 general_jrx_ctrl_1 [7:3 ] reserved reserved. 0x0 r [2:0] subclassv_ local jesd204b subclass. 0x1 r/w 000 subclass 0 001 subclass 1 0x302 dyn_link_latency_0 [7:5 ] reserved reserved. 0x0 r [4:0] dyn_link_ latency_0 dynamic link latency: link 0. latency between the lmfc rx for link 0 and the last arriving lmfc boundary in units of pclk cycles. see the deterministic latency section. 0x0 r 0x303 dyn_link_latency_1 [7:5 ] reserved reserved. 0x0 r [4:0] dyn_link_ latency_1 dynamic link latency: link 1. latency between the lmfc rx for link 1 and the last arriving lmfc boundary in units of pclk cycles. see the deterministic latency section. 0x0 r 0x304 lmfc_delay_0 [7:5] re served reserved. 0x0 r [4:0] lmfc_delay_0 lmfc delay: link 0 delay from the lmfc to lmfc rx for link 0. in units of frame clock cycles for subclass 1 and pclk cycles for subclass 0. see the deterministic latency section. 0x0 r/w 0x305 lmfc_delay_1 [7:5] re served reserved. 0x0 r [4:0] lmfc_delay_1 lmfc delay: link 1. delay from the lmfc to lmfc rx for link 1. in units of frame clock cycles for subclass 1 and pclk cycles for subclass 0. see the deterministic latency section. 0x0 r/w 0x306 lmfc_var_0 [7:5] re served reserved. 0x0 r [4:0] lmfc_var_0 variable delay buffer: link 0. sets when data is read from a buffer to be consistent across links and power cycles. in units of pclk cycles. see the deterministic latency section. this setting must not be more than 10. 0x6 r/w 0x307 lmfc_var_1 [7:5] re served reserved. 0x0 r [4:0] lmfc_var_1 variable delay buffer: link 1. sets when data is read from a buffer to be consistent across links and power cycles. in units of pclk cycles. see the deterministic latency section. this setting must not be more than 10. 0x6 r/w
ad9144 data sheet rev. a | page 114 of 125 address name bit no. bit name settings description reset access 0x308 xbar_ln_0_1 [7:6] re served reserved. 0x0 r [5:3] logical_lane1_ src logical lane 1 source. selects a physical lane to be mapped onto logical lane 1. 0x1 r/w x data is from serdinx [2:0] logical_lane0_ src logical lane 0 source. selects a physical lane to be mapped onto logical lane 0. 0x0 r/w x data is from serdinx 0x309 xbar_ln_2_3 [7:6] re served reserved. 0x0 r [5:3] logical_lane3_ src logical lane 3 source. selects a physical lane to be mapped onto logical lane 3. 0x3 r/w x data is from serdinx [2:0] logical_lane2_ src logical lane 2 source. selects a physical lane to be mapped onto logical lane 2. 0x2 r/w x data is from serdinx 0x30a xbar_ln_4_5 [7:6] re served reserved. 0x0 r [5:3] logical_lane5_ src logical lane 5 source. selects a physical lane to be mapped onto logical lane 5. 0x5 r/w x data is from serdinx [2:0] logical_lane4_ src logical lane 4 source. selects a physical lane to be mapped onto logical lane 4. 0x4 r/w x data is from serdinx 0x30b xbar_ln_6_7 [7:6] re served reserved. 0x0 r [5:3] logical_lane7_ src logical lane 7 source. selects a physical lane to be mapped onto logical lane 7. 0x7 r/w x data is from serdinx [2:0] logical_lane6_ src logical lane 6 source. selects a physical lane to be mapped onto logical lane 6. 0x6 r/w x data is from serdinx 0x30c fifo_status_reg_0 [7:0] lane_fifo_full fifo full flags for each logical lane. a full fifo indicates an error in the jesd204b configuration or with a system clock. 0x0 r if the fifo for lane x is full, bit x in this register will be high. 0x30d fifo_status_reg_1 [7:0] lane_fifo_empty fifo empty flags for each logical lane. an empty fifo indicates an error in the jesd204b configuration or with a system clock. 0x0 r if the fifo for logical lane x is empty, bit x in this register will be high. 0x312 syncb_gen_1 [7:6] rese rved reserved. 0x0 r/w [5:4] syncb_err _dur duration of syncoutx low for error. the duration applies to both syncout0 and syncout1 . a sync error is asserted at the end of a multiframe whenever one or more disparity, not in table or unexpected control character errors are encountered. 0 ? pclk cycle 1 1 pclk cycle 2 2 pclk cycles [3:0] reserved reserved. 0x0 r/w 0x314 serdes_spi_reg [7:0] serdes_spi_ config serdes spi configuration. must be written to 0x01 as part of the physical layer setup step. 0x0 r/w 0x315 phy_prbs_test_en [7:0] phy_test_en phy test enable. enables th e phy ber test. 0x0 r/w set bit x to enable the phy test for lane x.
data sheet ad9144 rev. a | page 115 of 125 address name bit no. bit name settings description reset access 0x316 phy_prbs_test_ctrl 7 reserved reserved. 0x0 r [6:4] phy_src_err_cnt phy error count source. selects which phy errors are being reported in register 0x31a to register 0x31c. 0x0 r/w x report lane x error count [3:2] phy_prbs_pat_sel phy prbs pattern select. selects the prbs pattern for phy ber test. 0x0 r/w 00 prbs7 01 prbs15 10 prbs31 1 phy_test_start phy prbs test start. starts and stops the phy prbs test. 0x0 r/w 0 test stopped 1 test in progress 0 phy_test_reset phy prbs te st reset. resets the phy prbs test state machine and error counters. 0x0 r/w 0 enable phy prbs test state machine 1 hold phy prbs test state machine in reset 0x317 phy_prbs_test_ threshold_lobits [7:0] phy_prbs_ threshold[7:0] 8 lsbs of phy prbs error threshold. 0x0 r/w 0x318 phy_prbs_test_ threshold_ midbits [7:0] phy_prbs_ threshold[15:8] 8 isbs of phy prbs error threshold. 0x0 r/w 0x319 phy_prbs_test_ threshold_hibits [7:0] phy_prbs_ threshold[23:16] 8 msbs of phy prbs error threshold. 0x0 r/w 0x31a phy_prbs_test_ errcnt_lobits [7:0] phy_prbs_err_ cnt[7:0] 8 lsbs of phy prbs error count. reported phy bert error count from lane selected using register 0x316[6:4]. 0x0 r 0x31b phy_prbs_test_ errcnt_midbits [7:0] phy_prbs_err_ cnt[15:8] 8 isbs of phy prbs error count. 0x0 r 0x31c phy_prbs_test_ errcnt_hibits [7:0] phy_prbs_err_ cnt[23:16] 8 msbs of phy prbs error count. 0x0 r 0x31d phy_prbs_test_ status [7:0] phy_prbs_pass phy prbs test pass/fail. 0xff r bit x corresponds to phy prbs pass/fail for physical lane x. the bit is set to 1 while the error count for physical lane x is less than phy_prbs_threshold. 0x32c short_tpl_test_0 [7:6] reserved reserved. 0x0 r [5:4] short_tpl_sp_ sel short transport layer sample select. selects which sample to check from the dac selected via bits[3:2]. 0x0 r/w x sample x [3:2] short_tpl_dac_ sel short transport layer test dac select. selects which dac to sample. 0x0 r/w x sample from dac x 1 short_tpl_test_ reset short transport layer test reset. resets the result of short transport layer test. 0x0 r/w 0 not reset 1 reset 0 short_tpl_test_ en short transport layer test enable. see the subclass 0 section for details on how to perform this test. 0x0 r/w 0 disable 1 enable 0x32d short_tpl_test_1 [7:0] short_tpl_ref_ sp_lsb short transport layer test reference, sample lsb. this is the lower eight bits of the expected dac sample. it is used to compare with the received dac sample at the output of the jesd204b receiver. 0x0 r/w
ad9144 data sheet rev. a | page 116 of 125 address name bit no. bit name settings description reset access 0x32e short_tpl_test_2 [7:0] short_tpl_ref_ sp_msb short transport layer test reference, sample msb. this is the upper eight bits of the expected dac sample. it is used to compare with the received dac sample at the output of the jesd204b receiver. 0x0 r/w 0x32f short_tpl_test_3 [7:1] reserved reserved. 0x0 r 0 short_tpl_fail short transpor t layer test fail. this bit shows whether the selected dac sample matches the reference sample. if they match, it is a test pass, otherwise it is a test fail. 0x0 r 0 test pass 1 test fail 0x333 device_config_ reg_13 [7:0] device_config_ 13 must be set to 0x01 for proper jesd interface configuration. 00 r/w 0x334 jesd_bit_inverse_ ctrl [7:0] jesd_bit_inverse logical lane invert. set bit x high to invert the jesd deserialized data on logical lane x. 0x0 r/w 0x400 did_reg [7:0] did_ rd device identification number. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x401 bid_reg [7:4] adjcnt_rd adjust ment resolution to dac lmfc. link information received on link lane 0 as specified in section 8.3 of jesd204b. must be 0. 0x0 r [3:0] bid_rd bank identification: extension to did. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x402 lid0_reg 7 reserved reserved. 0x0 r 6 adjdir_rd direction to adjust dac lmfc. link information received on link lane 0 as specified in section 8.3 of jesd204b. must be 0. 0x0 r 5 phadj_rd phase adjustment request to dac link information received on link lane 0 as specified in section 8.3 of jesd204b. must be 0. 0x0 r [4:0] lid0_rd lane identification for lane 0. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x403 scr_l_reg 7 scr_rd transmit scrambling status. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 scrambling is disabled 1 scrambling is enabled [6:5] reserved reserved. 0x0 r [4:0] l-1_rd number of lanes per converter device. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 one lane per converter 1 two lanes per converter 3 four lanes per converter 0x404 f_reg [7:0] f-1_rd number of octets per frame. settings of 1, 2 and 4 octets per frame are valid. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 (one octet per frame) per lane 1 (two octets per frame) per lane 3 (four octets per frame) per lane
data sheet ad9144 rev. a | page 117 of 125 address name bit no. bit name settings description reset access 0x405 k_reg [7:5 ] reserved reserved. 0x0 r [4:0] k-1_rd number of frames per multiframe. settings of 16 or 32 are valid. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x0f 16 frames per multiframe 0x1f 32 frames per multiframe 0x406 m_reg [7:0] m-1_rd number of converters per device. link information received on link lane 0 as specified in section 8.3 of jesd204b. must be 0, 1, or 3. 0x0 r 0 one converter per device 1 two converters per device 3 four converters per device 0x407 cs_n_reg [7:6] cs_rd number of control bits per sample. link information received on link lane 0 as specified in section 8.3 of jesd204b. cs must be 0. 0x0 r 5 reserved reserved. 0x0 r [4:0] n-1_rd converter resolution. link information received on link lane 0 as specified in section 8.3 of jesd204b. converter resolution must be 16. 0x0 r 0x0f converter resolution of 16 0x408 np_reg [7:5] subclassv_rd device subclass version. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r [4:0] np-1_rd total number of bits per sample. link information received on link lane 0 as specified in section 8.3 of jesd204b. must be 16 bits per sample. 0x0 r 0x0f 16 bits per sample. 0x409 s_reg [7:5] jesdv_rd jesd204 version. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 000 jesd204a 001 jesd204b [4:0] s-1_rd number of samples per converter per frame cycle. settings of one and two are valid. see table 35 and table 36. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 one sample per converter per frame 1 two samples per converter per frame 0x40a hd_cf_reg 7 hd_rd high density format. see section 5.1.3 of the jesd294b standard. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 low density mode 1 high density mode: link information received on lane 0 as specified in section 8.3 of jesd204b [6:5] reserved reserved. 0x0 r [4:0] cf_rd number of control words per frame clock period per link. link information received on link lane 0 as specified in section 8.3 of jesd204b. bits[4:0] must be 0. 0x0 r 0x40b res1_reg [7:0] res1_rd reserved field 1. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r
ad9144 data sheet rev. a | page 118 of 125 address name bit no. bit name settings description reset access 0x40c res2_reg [7:0] res2_rd reserved field 2. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x40d checksum_reg [7:0] fchk0_rd checksum for link lane 0. link information received on link lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x40e compsum0_reg [7:0] fc mp0_rd computed checksum for link lane 0. the jesd204b receiver computes the checksum of the link information received on lane 0 as specified in section 8.3 of jesd204b. the computation method is set by the checksum_mode bit (address 0x300[6]) and must match the likewise calculated checksum in register 0x40d. 0x0 r 0x412 lid1_reg [7:5] rese rved reserved. 0x0 r [4:0] lid1_rd lane identification for link lane 1.link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x415 checksum1_reg [7:0] fchk1_rd checks um for link lane 1. link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x416 compsum1_reg [7 :0] fcmp1_rd computed checks um for link lane 1. see the description for register 0x40e. 0x0 r 0x41a lid2_reg [7:5] rese rved reserved. 0x0 r [4:0] lid2_rd lane identification for link lane 2. 0x0 r 0x41d checksum2_reg [7:0] fchk2_rd checksum for link lane 2. 0x0 r 0x41e compsum2_reg [7:0] fc mp2_rd computed checksum for link lane 2 (see the description for register 0x40e). 0x0 r 0x422 lid3_reg [7:5] rese rved reserved. 0x0 r [4:0] lid3_rd lane identification for link lane 3. 0x0 r 0x425 checksum3_reg [7:0] fchk3_rd checksum for link lane 3. 0x0 r 0x426 compsum3_reg [7 :0] fcmp3_rd computed checksum for link lane 3 (see the description for register 0x40e). 0x0 r 0x42a lid4_reg [7:5] rese rved reserved. 0x0 r [4:0] lid4_rd lane identification for link lane 4. 0x0 r 0x42d checksum4_reg [7:0] fchk4_rd checksum for link lane 4. 0x0 r 0x42e compsum4_reg [7:0] fc mp4_rd computed checksum for link lane 4 (see the description for register 0x40e). 0x0 r 0x432 lid5_reg [7:5] rese rved reserved. 0x0 r [4:0] lid5_rd lane identification for link lane 5. 0x0 r 0x435 checksum5_reg [7:0] fchk5_rd checksum for link lane 5. 0x0 r 0x436 compsum5_reg [7 :0] fcmp5_rd computed checksum for link lane 5 (see the description for register 0x40e). 0x0 r 0x43a lid6_reg [7:5] rese rved reserved. 0x0 r [4:0] lid6_rd lane identification for link lane 6. 0x0 r 0x43d checksum6_reg [7:0] fchk6_rd checksum for link lane 6. 0x0 r 0x43e compsum6_reg [7:0] fc mp6_rd computed checksum for link lane 6 (see the description for register 0x40e). 0x0 r 0x442 lid7_reg [7:5] rese rved reserved. 0x0 r [4:0] lid7_rd lane identification for link lane 7. 0x0 r 0x445 checksum7_reg [7:0] fchk7_rd checksum for link lane 7. 0x0 r 0x446 compsum7_reg [7 :0] fcmp7_rd computed checksum for link lane 7 (see the description for register 0x40e). 0x0 r 0x450 ils_did [7:0] did device identification number. link information received on link lane 0 as specified in section 8.3 of jesd204b. must be set to value read in register 0x400. 0x0 r/w
data sheet ad9144 rev. a | page 119 of 125 address name bit no. bit name settings description reset access 0x451 ils_bid [7:4] adjcnt adjustment resolution to dac lmfc must be set to 0. 0x0 r/w [3:0] bid bank identification: extension to did must be set to value read in register 0x401[3:0]. 0x0 r/w 0x452 ils_lid0 7 reserv ed reserved. 0x0 r 6 adjdir direction to adjust dac lmfc. must be set to 0. 0x0 r/w 5 phadj phase adjustment request to dac. must be set to 0. 0x0 r/w [4:0] lid0 lane identification for link lane 0. must be set to the value read in register 0x402[4:0]. 0x0 r/w 0x453 ils_scr_l 7 scr receiver descrambling enable. 0x1 r/w 0 descrambling is disabled 1 descrambling is enabled [6:5] reserved reserved. 0x0 r [4:0] l-1 number of lanes per converter device. see table 35 and table 36. 0x3 r/w 0 one lane per converter 1 two lanes per converter 3 four lanes per converter 7 eight lanes per converter (single link only) 0x454 ils_f [7:0] f-1 number of octets per lane per frame. settings of 1, 2, and 4 (octets per lane) per frame are valid. see table 35 and table 36. 0x0 r/w 0 (one octet per lane) per frame 1 (two octets per lane) per frame 3 (four octets per lane) per frame 0x455 ils_k [7:5] reserv ed reserved. 0x0 r [4:0] k-1 number of frames per multiframe. settings of 16 or 32 are valid. must be set to 32 when f = 1 (register 0x476). 0x1f r/w 0x0f 16 frames per multiframe 0x1f 32 frames per multiframe 0x456 ils_m [7:0] m-1 number of converters per device. see table 35 and table 36. 0x1 r/w 0 one converter per link 1 two converters per link 3 four converters per link (single link only) 0x457 ils_cs_n [7:6] cs number of control bits per sample. must be set to 0. control bits are not supported. 0x0 r/w 0 zero control bits per sample 5 reserved reserved. 0x0 r [4:0] n-1 converter resolution. must be set to 16 bits of resolution. 0xf r/w 0xf converter resolution of 16. 0x458 ils_np [7:5] subclassv device subclass version. 0x1 r/w 0 subclass 0 1 subclass 1 [4:0] np-1 total number of bits per sample. must be set to 16 bits per sample. 0xf r/w 0xf 16 bits per sample. 0x459 ils_s [7:5] jesdv jesd204 version. 0x1 r/w 000 jesd204a 001 jesd204b [4:0] s-1 number of samples per converter per frame cycle. settings of one and two are valid. see table 35 and table 36. 0x0 r/w 0 one sample per converter per frame 1 two samples per converter per frame
ad9144 data sheet rev. a | page 120 of 125 address name bit no. bit name settings description reset access 0x45a ils_hd_cf 7 hd high density format. if f = 1, hd must be set to 1. otherwise, hd must be set to 0. see section 5.1.3 of jesd204b standard. 0x1 r/w 0 low density mode 1 high density mode [6:5] reserved reserved. 0x0 r [4:0] cf number of control words per frame clock period per link. must be set to 0. control bits are not supported. 0x0 r/w 0x45b ils_res1 [7:0] res1 reserved field 1. 0x0 r/w 0x45c ils_res2 [7:0] res2 reserved field 2. 0x0 r/w 0x45d ils_checksum [7:0] fchk0 checksum for link lane 0. calculated checksum. calculation depends on 0x300[6]. 0x45 r/w 0x46b errcntrmon_rb [7:0] read errorcntr read jesd204b error counter. after selecting the lane and error counter by writing to lanesel and cntrsel (both in this same register), the selected error counter is read back here. 0x0 r 0x46b errcntrmon 7 reserved reserved. 0x0 r [6:4] lanesel link lane sele ct for jesd204b error counter. selects the lane whose errors are read back in this register. 0x0 w x selects link lane x [3:2] reserved reserved. 0x0 r [1:0] cntrsel jesd204b error counter select. selects the type of error that are read back in this register. 0x0 w 00 baddiscntr: bad running disparity counter 01 nitcntr: not in table error counter 10 ucccntr: unexpected control character counter 0x46c lanedeskew [7:0] lanedeskew lane deskew. setting bit x deskews link lane x 0xf r/w 0x46d baddisparity_rb [7:0] baddis bad disparity character error (baddis). bit x is set when the bad disparity error count for link lane x reaches the threshold in register 0x47c. 0x0 r 0x46d baddisparity 7 rst_irq_dis baddis irq reset. reset baddis irq for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 6 disable_err_ cntr_dis baddis error counter disable. disable the baddis error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 5 rst_err_cntr_dis baddis error counter reset. reset baddis error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w [4:3] reserved reserved. 0x0 r [2:0] lane_addr_dis link lane address for functions described in bits[7:5]. 0x0 w 0x46e nit_rb [7:0] nit not in tabl e character error (nit). bit x is set when the nit error count for link lane x reaches the threshold in register 0x47c. 0x0 r 0x46e nit_w 7 rst_irq_nit irq reset. reset irq for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 6 disable_err_ cntr_nit disable error counter. disable the error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 5 rst_err_cntr_nit reset error co unter. reset error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w [4:3] reserved reserved. 0x0 r [2:0] lane_addr_nit link lane address for functions described in bits[7:5]. 0x0 w
data sheet ad9144 rev. a | page 121 of 125 address name bit no. bit name settings description reset access 0x46f unexpected- control_rb [7:0] ucc unexpected co ntrol character error (ucc). bit x is set when the ucc error count for link lane x reaches the threshold in register 0x47c. 0x0 r 0x46f unexpected- control_w 7 rst_irq_ucc irq reset. reset irq for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 6 disable_err_ cntr_ucc disable error counter. disable the error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w 5 rst_err_cntr_ ucc reset error counter. reset error counter for lane selected via bits[2:0] by writing 1 to this bit. 0x0 w [4:3] reserved reserved. 0x0 r [2:0] lane_addr_ucc link lane address for functions described in bits[7:5]. 0x0 w 0x470 codegrpsyncflg [7:0] codegrpsync code group sync flag (from each instantiated lane). writing 1 to bit 7 resets the irq. the associated irq flag is located in register 0x47a[0]. a loss of codegrpsync triggers sync request assertion. see the syncout and sysref signals section and the deterministic latency section. 0x0 r/w 0 synchronization is lost 1 synchronization is achieved 0x471 framesyncflg [7:0] framesync fram e sync flag (from each instantiated lane). this register indicates the live status for each lane. writing 1 to bit 7 resets the irq. a loss of frame sync automatically initiates a synchronization sequence. 0x0 r/w 0 synchronization is lost 1 synchronization is achieved 0x472 goodchksumflg [7:0] goodchecksum good checksum flag (from each instantiated lane). writing 1 to bit 7 resets the irq. the associated irq flag is located in register 0x47a[2]. 0x0 r/w 0 last computed checksum is not correct 1 last computed checksum is correct 0x473 initlanesyncflg [7:0] initiallanesync init ial lane sync flag (from each instantiated lane). writing 1 to bit 7 resets the irq. the associated irq flag is located in register 0x47a[3]. loss of synchronization is also reported on syncout1 or syncout0 . see the syncout and sysref signal section and the deterministic latency section. 0x0 r/w 0x476 ctrlreg1 [7:0] f number of oc tets per frame. settings of 1, 2, and 4 are valid. see table 35 and table 36. 0x1 r/w 1 one octet per frame 2 two octets per frame 4 four octets per frame 0x477 ctrlreg2 7 ilas_mode ilas test mode. defined in section 5.3.3.8 of jesd204b specification. 0x0 r/w 1 jesd204b receiver is constantly receiving ilas frames 0 normal link operation [6:4] reserved reserved. 0x0 r 3 threshold_ mask_en threshold mask enable. set this bit if using sync_assertion_mask (register 0x47b[7:5]). 0x0 r/w [2:0] reserved reserved. 0x0 r 0x478 kval [7:0] ksync number of k multiframes during ilas (divided by four). sets the number of multiframes to send initial lane alignment sequence. cannot be set to 0. 0x1 r/w x 4x multiframes during ilas
ad9144 data sheet rev. a | page 122 of 125 address name bit no. bit name settings description reset access 0x47a irqvector_mask 7 baddis_mask bad disparity mask. 0x0 w 1 if the bad disparity count reaches errorthresh on any lane, irq is pulled low. 6 nit_mask not in table mask. 0x0 w 1 if the not in table character count reaches errorthresh on any lane, irq is pulled low. 5 ucc_mask unexpected control character mask. 0x0 w 1 if the unexpected control character count reaches errorthresh on any lane, irq is pulled low. 4 reserved reserved. 0x0 r 3 initiallanesync_ mask initial lane sync mask. 0x0 w 1 if initial lane sync (0x473) fails on any lane, irq is pulled low. 2 badchecksum_ mask bad checksum mask. 0x0 w 1 if there is a bad checksum (0x472) on any lane, irq is pulled low. 1 framesync_ mask frame sync mask 0x0 w 1 if frame sync (0x471) fails on any lane, irq is pulled low. 0 codegrpsync_ mask code group sync machine mask. 0x0 w 1 if code group sync (0x470) fails on any lane, irq is pulled low. 0x47a irqvector_flag 7 baddis_flag bad disparity error count. 0x0 r 1 bad disparity character count reached errorthresh (0x47c) on at least one lane. read register 0x46d to determine which lanes are in error. 6 nit_flag not in table error count 0x0 r 1 not in table character count reached errorthresh (0x47c) on at least one lane. read register 0x46e to determine which lanes are in error. 5 ucc_flag unexpected co ntrol character e rror count 0x0 r 1 unexpected control character count reached errorthresh (0x47c) on at least one lane. read register 0x46f to determine which lanes are in error. 4 reserved reserved. 0x0 r 3 initiallanesync_ flag initial lane sync flag. 0x0 r 1 initial lane sync failed on at least one lane. read register 0x473 to determine which lanes are in error 2 badchecksum_ flag bad checksum flag. 0x0 r 1 bad checksum on at least one lane. read register 0x472 to determine which lanes are in error. 1 framesync_ flag frame sync flag. 0x0 r 1 frame sync failed on at least one lane. read register 0x471 to determine which lanes are in error. 0 codegrpsync_ flag code group sync flag. 0x0 r 1 code group sync failed on at least one lane. read register 0x470 to determine which lanes are in error
data sheet ad9144 rev. a | page 123 of 125 address name bit no. bit name settings description reset access 0x47b syncassertionmask 7 baddis_s bad disparity error on sync. 0x0 r/w 1 asserts a sync request on syncoutx when the bad disparity character count reaches the threshold in register 0x47c 6 nit_s not in table error on sync. 0x0 r/w 1 asserts a sync request on syncoutx when the not in table character count reaches the threshold in register 0x47c 5 ucc_s unexpected control character error on sync. 0x0 r/w 1 asserts a sync request on syncoutx when the unexpected control character count reaches the threshold in register 0x47c 4 cmm configuration mismatch irq. if cmm_enable is high, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. if cmm_enable is low, this bit is non-functional. 0x0 r/w 1 link lane 0 configuration registers (register 0x450 to register 0x45d) do not match the jesd204b transmit settings (register 0x400 to register 0x40d) 3 cmm_enable configuration mismatch irq enable. 0x1 r/w 1 enables irq generation if a configuration mismatch is detected 0 configuration mismatch irq disabled [2:0] reserved reserved. 0x0 r 0x47c errorthres [7:0] eth error thre shold. bad disparity, not in table, and unexpected contro l character errors are counted and compared to the error threshold value. when the count reaches the threshold, either an irq is generated or the syncoutx signal is asserted per the mask register settings, or both. function is performed in all lanes. 0xff r/w 0x47d laneenable [7:0] lane_ena lane enable. setting bit x enables link lane x. this register must be programmed before receiving the code group pattern for proper operation. 0xf r/w 0x47e ramp_ena [7:1] rese rved reserved. 0x0 r 0 ena_ramp_ check enable ramp checking at the beginning of ilas. 0x0 w 0 disable ramp checking at beginning of ilas; ilas data need not be a ramp 1 enable ramp checking; ilas data needs to be a ramp starting at 00-01-02; otherwise, the ramp ilas fails and the device does not start up 0x520 dig_test0 [7:2] reserved mu st write default value for proper operation. 0x7 r/w 1 dc_test_mode dc test mode 0x0 r/w 0 reserved reserved. 0x0 r/w 0x521 dc_test_valuei0 [7:0] dc_test_ valuei[7:0] dc value lsb of dc test mode for i dac. 0x0 r/w 0x522 dc_test_valuei1 [7:0] dc_test_ valuei [15:8] dc value msb of dc test mode for i dac. 0x0 r/w 0x523 dc_test_valueq0 [7:0] dc_test_ valueq[7:0] dc value lsb of dc test mode for q dac. 0x0 r/w 0x524 dc_test_valueq1 [7:0] dc_test_ valueq[15:8] dc value msb of dc test mode for q dac. 0x0 r/w
ad9144 data sheet rev. a | page 124 of 125 outline dimensions compliant to jedec standards mo-220-vrrd 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.28 0.23 0.18 10.50 ref 0.60 max 0.60 max 7.55 7.40 sq 7.25 0.50 bsc 0.20 ref 12 max seating plane pin 1 indicator 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indicator top view 0.90 0.85 0.80 exposed pad bottom view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 12.10 12.00 sq 11.90 11.85 11.75 sq 11.65 08-10-2012-a figure 88. 88-lead lead frame chip scale package [lfcsp_vq] 12 mm 12 mm body, very thin quad (cp-88-6) dimensions shown in millimeters compliant to jedec standards mo-220 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.80 0.70 0.60 1.00 0.90 0.80 0.65 0.55 0.45 0.30 0.25 0.20 10.50 ref 0.60 max 0.60 max 7.55 7.40 sq 5.25 0.50 bsc 0.190~0.245 ref 12 max seating plane pin 1 indicator 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indicator top view 0.90 0.85 0.80 exposed pad bottom view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 12.10 12.00 sq 11.90 11.85 11.75 sq 11.65 08-04-2014-a pkg-004598 figure 89. 88-lead lead frame chip scale package [lfcsp_vq] (variable lead length) 12 mm 12 mm body, very thin quad (cp-88-9) dimensions shown in millimeters
data sheet ad9144 rev. a | page 125 of 125 ordering guide model 1 temperature range package description package option ad9144bcpz ?40c to +85c 88-lead lfcsp_vq cp-88-6 ad9144bcpzrl ?40c to +85c 88-lead lfcsp_vq cp-88-6 AD9144BCPAZ ?40c to +85c 88-lead lfcsp_vq (variable lead length) cp-88-9 AD9144BCPAZrl ?40c to +85c 88-lead lfcsp_vq (variable lead length) cp-88-9 ad9144-ebz dpg3 evaluation board ad9144-fmc-ebz fmc evaluation board ad9144-m6720-ebz dpg3 evaluation board with adrf6720 modulator 1 z = rohs compliant part. ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11675-0-6/15(a)

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